add bin file download demo through esp8266 module

board/TencentOS_tiny_EVB_MX_Plus/KEIL/bin_file_download_through_module/startup_stm32l431xx.s

+;********************** COPYRIGHT(c) 2017  STMicroelectronics ******************
+;* File Name          : startup_stm32l431xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x100
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler                   ; ADC1
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     0                                 ; Reserved
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     0                                 ; Reserved
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                 ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     0                                 ; Reserved
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_IRQHandler                   [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+SDMMC1_IRQHandler
+SPI3_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+CRS_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

devices/esp8266/esp8266.c

@@ -174,7 +174,7 @@ static int esp8266_recv_timeout(int id, void *buf, size_t len, uint32_t timeout)
 
 static int esp8266_recv(int id, void *buf, size_t len)
 {
-    return esp8266_recv_timeout(id, buf, len, (uint32_t)4000);
+    return tos_at_channel_read(id, buf, len);
 }
 
 static int esp8266_is_link_broken(const char *echo_buffer)
@@ -435,6 +435,9 @@ __STATIC__ void esp8266_incoming_data_process(void)
         if (tos_at_uart_read(buffer, read_len) != read_len) {
             return;
         }
+        
+        //delay has two reason, wait for the data to be cached and untrigger scheduling
+        tos_stopwatch_delay(200);
 
         if (tos_at_channel_write(channel_id, buffer, read_len) <= 0) {
             return;
@@ -446,6 +449,7 @@ __STATIC__ void esp8266_incoming_data_process(void)
 
 at_event_t esp8266_at_event[] = {
     { "+IPD,", esp8266_incoming_data_process },
+    { "PD,", esp8266_incoming_data_process },
 };
 
 sal_module_t sal_module_esp8266 = {

examples/bin_file_download_through_module/bin_file_download_through_module.c

+#include "mcu_init.h"
+#include "sal_module_wrapper.h"
+
+#define USE_ESP8266
+
+#ifdef USE_ESP8266
+#include "esp8266.h"
+#endif
+
+#define HTTP_REQUEST_TEMPLATE       \
+"GET /%s HTTP/1.1\r\nAccept:*/*\r\n\
+User-Agent: Mozilla/5.0\r\n\
+Cache-Control: no-cache\r\n\
+Connection: close\r\n\
+Host:%s:%d\r\n\r\n"
+
+#define HOST_MAX            32
+#define FILE_MAX            32
+#define PORT_MAX            5
+#define HTTP_REQUEST_MAX    (sizeof(HTTP_REQUEST_TEMPLATE) + HOST_MAX + FILE_MAX + PORT_MAX)
+
+#define HTTP_RESPONSE_STATUS_CODE_OK        200
+
+typedef enum http_parse_status_en {
+    HTTP_PARSE_STATUS_NONE,
+    HTTP_PARSE_STATUS_BLANK_LINE,
+    HTTP_PARSE_STATUS_HEADER,
+    HTTP_PARSE_STATUS_OVERFLOW,
+    HTTP_PARSE_STATUS_TIMEOUT,
+} http_parse_status_t;
+
+static uint16_t ota_str2uint16(char *str)
+{
+    uint16_t r = 0;
+
+    while (*str) {
+        r = r * 10 + *str++ - '0';
+    }
+
+    return r;
+}
+
+static int ota_url_parse(char *url, char *host, uint16_t *port, char *file)
+{
+    /* http://192.168.1.107:80/test_2048.bin */
+    char *p;
+    int len;
+    static char the_port[PORT_MAX + 1];
+
+    /* 1. skip http url prefix */
+#define HTTP_URL_PREFIX         "http://"
+    if (strncmp(url, HTTP_URL_PREFIX, strlen(HTTP_URL_PREFIX)) != 0) {
+        return -1;
+    }
+
+    url += strlen(HTTP_URL_PREFIX);
+
+    /* 2. parse host */
+    p = strstr(url, ":");
+    if (!p || (len = p - url) > HOST_MAX) { /* ":" not found or host name too long */
+        return -1;
+    }
+
+    strncpy(host, url, len);
+    host[len] = '\0';
+
+    /* 3. parse port */
+    url = p + 1;
+    p = strstr(url, "/");
+    if (!p || (len = p - url) > PORT_MAX) { /* ":" not found or port too long */
+        return -1;
+    }
+
+    strncpy(the_port, url, len);
+    the_port[len] = '\0';
+    *port = ota_str2uint16(the_port);
+
+    /* 4. parse file */
+    url = p + 1;
+    if (strlen(url) > FILE_MAX) {
+        return -1;
+    }
+    strcpy(file, url);
+
+    return 0;
+}
+
+static void ota_http_request_construct(char *http_request, char *host, uint16_t port, char *file)
+{
+    snprintf(http_request, HTTP_REQUEST_MAX, HTTP_REQUEST_TEMPLATE, file, host, port);
+}
+
+static http_parse_status_t ota_http_response_line_parse(int fd, char *line_buf, size_t buf_len)
+{
+    size_t curr_len = 0;
+    k_stopwatch_t stopwatch;
+    uint8_t data, last_data = 0;
+
+    memset(line_buf, 0, buf_len);
+
+    tos_stopwatch_create(&stopwatch);
+    tos_stopwatch_countdown_ms(&stopwatch, 8000);
+    while (K_TRUE) {
+        if (tos_stopwatch_is_expired(&stopwatch)) {
+            return HTTP_PARSE_STATUS_TIMEOUT;
+        }
+
+        if (curr_len >= buf_len) {
+             return HTTP_PARSE_STATUS_OVERFLOW;
+        }
+
+        if (tos_sal_module_recv_timeout(fd, &data, 1, 1000) <= 0) {
+            continue;
+        }
+
+        if (data == '\n' && last_data == '\r') {
+            curr_len -= 1;
+            line_buf[curr_len] = '\0';
+
+            if (curr_len == 0) {
+                return HTTP_PARSE_STATUS_BLANK_LINE;
+            }
+
+            return HTTP_PARSE_STATUS_HEADER;
+        }
+
+        line_buf[curr_len++] = data;
+        last_data = data;
+    }
+}
+
+static void hex_dump(uint8_t *buf, size_t len)
+{
+    uint16_t i;
+    
+    for (i = 0; i < len; i++) {
+        printf("%02x ", buf[i]);
+        if ((i+1) % 16 == 0) {
+            printf("\r\n");
+        }
+    }
+}
+
+static int ota_http_body_read(int fd, int file_len, unsigned char *buf, size_t buf_len)
+{
+    int remain_len = file_len, read_len;
+    int ret;
+    
+#define MIN(a, b)       ((a) < (b) ? (a) : (b))
+    
+    printf("file_len is %d,  remain_len = %d\r\n", file_len, read_len);
+    
+    while (remain_len > 0) {
+        read_len = MIN(remain_len, buf_len);
+        
+        printf("remain_len is %d\r\n", remain_len);
+        
+        if ((ret = tos_sal_module_recv(fd, buf, read_len)) != read_len) {
+            printf("tos_sal_module_recv fail, ret is %d\r\n", ret);
+            
+            return -1;
+        }
+        
+        printf("tos_sal_module_recv success, read_len is %d\r\n", read_len);
+
+        hex_dump(buf, read_len);
+
+        remain_len -= read_len;
+    }
+
+    return 0;
+}
+
+static int ota_http_response_parse(int fd)
+{
+#define HTTP_HEADER_MAX         128
+#define HEADER_FIELD_MAX        30
+    static char line_buf[HTTP_HEADER_MAX];
+    static char header_field[HEADER_FIELD_MAX];
+
+    http_parse_status_t status;
+    int header_value, file_len;
+    int is_response_status_ok = K_FALSE;
+
+    do {
+        printf("line buf:[%s]\r\n", line_buf);
+        status = ota_http_response_line_parse(fd, line_buf, sizeof(line_buf));
+
+        if (strncmp("HTTP/", line_buf, strlen("HTTP/")) == 0) {
+            sscanf(line_buf, "%s %d", header_field, &header_value);
+            if (header_value != HTTP_RESPONSE_STATUS_CODE_OK) {
+                return -1;
+            }
+
+            is_response_status_ok = K_TRUE;
+        } else if (strncmp("Content-Length:", line_buf, strlen("Content-Length:")) == 0) {
+            sscanf(line_buf, "%s %d", header_field, &header_value);
+            file_len = header_value;
+        }
+    } while (status == HTTP_PARSE_STATUS_HEADER);
+
+    if (!is_response_status_ok) {
+        return -1;
+    }
+
+    if (status == HTTP_PARSE_STATUS_OVERFLOW ||
+        status == HTTP_PARSE_STATUS_TIMEOUT ||
+        file_len <= 0) {
+        return -1;
+    }
+
+    /* must be HTTP_PARSE_STATUS_BLANK_LINE, means the body begins */
+    if (ota_http_body_read(fd, file_len, (unsigned char *)line_buf, sizeof(line_buf)) < 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+void application_entry(void *arg)
+{
+    int fd;
+    int ret;
+    char host[HOST_MAX];
+    char port[PORT_MAX];
+    char file[FILE_MAX];
+    uint16_t port_num;
+    char http_request[HTTP_REQUEST_MAX];
+    
+    /* The different size test bin files is supported in example folder */
+    char *url = "http://192.168.1.107:80/test_2048.bin";
+
+#if defined(USE_ESP8266)
+    esp8266_sal_init(HAL_UART_PORT_0);
+    esp8266_join_ap("Tencent-WIFI", "424424424");
+#endif
+    
+    ret = ota_url_parse(url, host, &port_num, file);
+    if (ret != 0) {
+        printf("url parser fail, ret is %d\r\n", ret);
+        return;
+    } else {
+        sprintf(port, "%d", port_num);
+        printf("url parser success:\r\n");
+        printf("  -host:%s\r\n", host);
+        printf("  -port:%s\r\n", port);
+        printf("  -file:%s\r\n", file);
+    }
+    
+    ota_http_request_construct(http_request, host, port_num, file);
+    
+    /* 1. connect to host */
+    fd = tos_sal_module_connect(host, port, TOS_SAL_PROTO_TCP); 
+    if (fd == -1) {
+        printf("TCP connect failed\r\n");
+    } else {
+        printf("TCP connect success! fd: %d\n", fd);
+    }
+    
+    /* 2. send http request */
+     if (tos_sal_module_send(fd, (void *)http_request, strlen(http_request)) < 0) {
+        printf("TCP send http request fail\r\n");
+        tos_sal_module_close(fd);
+        return;
+    } else {
+        printf("TCP send http request success\r\n");
+    }
+    
+    /* 3. parse http response */
+    ret = ota_http_response_parse(fd);
+
+    /* 4. free socket */
+    tos_sal_module_close(fd);
+    printf("TCP disconnect success!\r\n");
+    
+     while (1) {
+        printf("ota http download finish!\r\n");
+        tos_task_delay(1000);
+    }
+
+}
+

net/socket_wrapper/tos_at_socket.c

@@ -98,13 +98,13 @@ int recv(int socket, void *buffer, size_t length, int flags)
     SOCKET_ID_SET_SANITY_CHECK(socket);
 
     if (!(flags & MSG_WAITALL)) {
-        return tos_sal_module_recv(socket_get_fd(socket), buffer, length);
+        return tos_sal_module_recv_timeout(socket_get_fd(socket), buffer, length, 4000);
     }
 
     while (total_len < length) {
-        recv_len = tos_sal_module_recv(socket_get_fd(socket),
+        recv_len = tos_sal_module_recv_timeout(socket_get_fd(socket),
                                         (uint8_t *)buffer + total_len,
-                                        remain_len);
+                                        remain_len, 4000);
 
         if (recv_len <= 0) {
             continue;