merge new qcloud sdk

1. qcloud has a great revolution, the protocol has been changed to implement data template, so the old TencentCloud_SDK developed by us will not work fine now(mqtt still works, but data template will not works fine for recently created product/devices).

2. I merge the official qlcoud sdk(include both the iot-hub and iot-explorer sdk) into the componet/conectivity to support new protocol of data template

3. iot-hub sdk, supply the fundamental iot protocol(like mqtt coap, etc.)
iot-explorer sdk, supply the high level service like data template based on mqtt

4. To know how it works, see qcloud_iot_explorer_sdk_data_template、qcloud_iot_hub_sdk_mqtt example(keil project in board\TencentOS_tiny_EVB_MX_Plus\KEIL\qcloud_iot_explorer_sdk_data_template and  board\TencentOS_tiny_EVB_MX_Plus\KEIL\qcloud_iot_hub_sdk_mqtt)

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_explorer_sdk_data_template/DebugConfig/TencentOS_tiny_STM32L431RCTx.dbgconf

+// File: STM32L43x_44x_45x_46x.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
+//       refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o0.2>    DBG_STANDBY
+//     <i> Debug Standby mode
+//     <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+//     <i> 1: (FCLK=On, HCLK=On) The digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.1>    DBG_STOP
+//     <i> Debug Stop mode
+//     <i> 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). 
+//     <i> 1: (FCLK=On, HCLK=On) When entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode.
+//   <o0.0>    DBG_SLEEP
+//     <i> Debug Sleep mode
+//     <i> 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled.
+//     <i> 1: (FCLK=On, HCLK=On) When entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//   <o0.31>    DBG_LPTIM1_STOP
+//     <i> LPTIM1 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
+//   <o0.25>    DBG_CAN_STOP
+//     <i> bxCAN1 stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The bxCAN1 receive registers are frozen
+//   <o0.23>    DBG_I2C3_STOP
+//     <i> I2C3 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C3 SMBus timeout is frozen
+//   <o0.22>    DBG_I2C2_STOP
+//     <i> I2C2 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C2 SMBus timeout is frozen
+//   <o0.21>    DBG_I2C1_STOP
+//     <i> I2C1 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C1 SMBus timeout is frozen
+//   <o0.12>    DBG_IWDG_STOP
+//     <i> Independent watchdog counter stopped when core is halted
+//     <i> 0: The independent watchdog counter clock continues even if the core is halted
+//     <i> 1: The independent watchdog counter clock is stopped when the core is halted
+//   <o0.11>    DBG_WWDG_STOP
+//     <i> Window watchdog counter stopped when core is halted
+//     <i> 0: The window watchdog counter clock continues even if the core is halted
+//     <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>    DBG_RTC_STOP
+//     <i> RTC counter stopped when core is halted
+//     <i> 0: The clock of the RTC counter is fed even if the core is halted
+//     <i> 1: The clock of the RTC counter is stopped when the core is halted
+//   <o0.5>    DBG_TIM7_STOP
+//     <i> TIM7 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM7 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM7 is stopped when the core is halted
+//   <o0.4>    DBG_TIM6_STOP
+//     <i> TIM6 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM6 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM6 is stopped when the core is halted
+//   <o0.0>    DBG_TIM2_STOP
+//     <i> TIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//   <o0.5>    DBG_LPTIM2_STOP
+//     <i> LPTIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//   <o0.17>    DBG_TIM16_STOP
+//     <i> TIM16 counter stopped when core is halted
+//     <i> 0: The clock of the TIM16 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM16 counter is stopped when the core is halted
+//   <o0.16>    DBG_TIM15_STOP
+//     <i> TIM15 counter stopped when core is halted
+//     <i> 0: The clock of the TIM15 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM15 counter is stopped when the core is halted
+//   <o0.11>    DBG_TIM1_STOP
+//     <i> TIM1 counter stopped when core is halted
+//     <i> 0: The clock of the TIM1 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM1 counter is stopped when the core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+// </h>
+
+// <<< end of configuration section >>>
\ No newline at end of file

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_explorer_sdk_data_template/EventRecorderStub.scvd

+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_explorer_sdk_data_template/RTE/_TencentOS_tiny/RTE_Components.h

+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'TencentOS_tiny' 
+ * Target:  'TencentOS_tiny' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32l4xx.h"
+
+
+#endif /* RTE_COMPONENTS_H */

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_explorer_sdk_data_template/obj/TencentOS_tiny.build_log.htm

+<html>
+<body>
+<pre>
+<h1>Vision Build Log</h1>
+<h2>Tool Versions:</h2>
+IDE-Version: Vision V5.26.2.0
+Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.26.2.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.26.2.0
+Dialog DLL:      DCM.DLL V1.17.2.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
+Dialog DLL:      TCM.DLL V1.36.1.0
+ 
+<h2>Project:</h2>
+D:\github\ble_dev\TencentOS-tiny\board\TencentOS_tiny_EVB_MX_Plus\KEIL\qcloud_iot_explorer_sdk_data_template\TencentOS_tiny.uvprojx
+Project File Date:  11/14/2019
+
+<h2>Output:</h2>
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'TencentOS_tiny'
+compiling data_template_sample.c...
+..\..\..\..\components\connectivity\qcloud-iot-explorer-sdk\3rdparty\include\exports\qcloud_iot_export_log.h(94): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Level();
+..\..\..\..\components\connectivity\qcloud-iot-explorer-sdk\3rdparty\include\exports\qcloud_iot_export_log.h(108): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Upload_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Upload_Level();
+..\..\..\..\examples\qcloud_iot_explorer_sdk_data_template\data_template_sample.c(35): warning:  #550-D: variable "sg_subscribe_event_result"  was set but never used
+  static MQTTEventType sg_subscribe_event_result = MQTT_EVENT_UNDEF;
+..\..\..\..\examples\qcloud_iot_explorer_sdk_data_template\data_template_sample.c: 3 warnings, 0 errors
+compiling HAL_Device_tencentos_tiny.c...
+..\..\..\..\components\connectivity\qcloud-iot-explorer-sdk\3rdparty\include\exports\qcloud_iot_export_log.h(94): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Level();
+..\..\..\..\components\connectivity\qcloud-iot-explorer-sdk\3rdparty\include\exports\qcloud_iot_export_log.h(108): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Upload_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Upload_Level();
+..\..\..\..\components\connectivity\qcloud-iot-explorer-sdk\port\TencentOS_tiny\HAL_Device_tencentos_tiny.c: 2 warnings, 0 errors
+linking...
+Program Size: Code=153492 RO-data=17516 RW-data=776 ZI-data=59048  
+FromELF: creating hex file...
+".\obj\TencentOS_tiny.axf" - 0 Error(s), 5 Warning(s).
+
+<h2>Software Packages used:</h2>
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
+                ARM.CMSIS.5.6.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.3.0
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack
+                Keil.STM32L4xx_DFP.2.0.0
+                STMicroelectronics STM32L4 Series Device Support, Drivers and Examples
+
+<h2>Collection of Component include folders:</h2>
+  .\RTE\_TencentOS_tiny
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
+  C:\Keil_v5\ARM\PACK\Keil\STM32L4xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include
+
+<h2>Collection of Component Files used:</h2>
+
+   * Component: ARM::CMSIS:CORE:5.3.0
+Build Time Elapsed:  00:00:03
+</pre>
+</body>
+</html>

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_explorer_sdk_data_template/obj/TencentOS_tiny.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_coap/DebugConfig/TencentOS_tiny_STM32L431RCTx.dbgconf

+// File: STM32L43x_44x_45x_46x.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
+//       refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o0.2>    DBG_STANDBY
+//     <i> Debug Standby mode
+//     <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+//     <i> 1: (FCLK=On, HCLK=On) The digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.1>    DBG_STOP
+//     <i> Debug Stop mode
+//     <i> 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). 
+//     <i> 1: (FCLK=On, HCLK=On) When entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode.
+//   <o0.0>    DBG_SLEEP
+//     <i> Debug Sleep mode
+//     <i> 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled.
+//     <i> 1: (FCLK=On, HCLK=On) When entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//   <o0.31>    DBG_LPTIM1_STOP
+//     <i> LPTIM1 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
+//   <o0.25>    DBG_CAN_STOP
+//     <i> bxCAN1 stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The bxCAN1 receive registers are frozen
+//   <o0.23>    DBG_I2C3_STOP
+//     <i> I2C3 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C3 SMBus timeout is frozen
+//   <o0.22>    DBG_I2C2_STOP
+//     <i> I2C2 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C2 SMBus timeout is frozen
+//   <o0.21>    DBG_I2C1_STOP
+//     <i> I2C1 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C1 SMBus timeout is frozen
+//   <o0.12>    DBG_IWDG_STOP
+//     <i> Independent watchdog counter stopped when core is halted
+//     <i> 0: The independent watchdog counter clock continues even if the core is halted
+//     <i> 1: The independent watchdog counter clock is stopped when the core is halted
+//   <o0.11>    DBG_WWDG_STOP
+//     <i> Window watchdog counter stopped when core is halted
+//     <i> 0: The window watchdog counter clock continues even if the core is halted
+//     <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>    DBG_RTC_STOP
+//     <i> RTC counter stopped when core is halted
+//     <i> 0: The clock of the RTC counter is fed even if the core is halted
+//     <i> 1: The clock of the RTC counter is stopped when the core is halted
+//   <o0.5>    DBG_TIM7_STOP
+//     <i> TIM7 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM7 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM7 is stopped when the core is halted
+//   <o0.4>    DBG_TIM6_STOP
+//     <i> TIM6 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM6 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM6 is stopped when the core is halted
+//   <o0.0>    DBG_TIM2_STOP
+//     <i> TIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//   <o0.5>    DBG_LPTIM2_STOP
+//     <i> LPTIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//   <o0.17>    DBG_TIM16_STOP
+//     <i> TIM16 counter stopped when core is halted
+//     <i> 0: The clock of the TIM16 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM16 counter is stopped when the core is halted
+//   <o0.16>    DBG_TIM15_STOP
+//     <i> TIM15 counter stopped when core is halted
+//     <i> 0: The clock of the TIM15 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM15 counter is stopped when the core is halted
+//   <o0.11>    DBG_TIM1_STOP
+//     <i> TIM1 counter stopped when core is halted
+//     <i> 0: The clock of the TIM1 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM1 counter is stopped when the core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+// </h>
+
+// <<< end of configuration section >>>
\ No newline at end of file

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_coap/EventRecorderStub.scvd

+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_coap/RTE/_TencentOS_tiny/RTE_Components.h

+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'TencentOS_tiny' 
+ * Target:  'TencentOS_tiny' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32l4xx.h"
+
+
+#endif /* RTE_COMPONENTS_H */

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_coap/obj/TencentOS_tiny.build_log.htm

+<html>
+<body>
+<pre>
+<h1>Vision Build Log</h1>
+<h2>Tool Versions:</h2>
+IDE-Version: Vision V5.26.2.0
+Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: sheldon dai, tencent, LIC=AK1CX-H5HPV-SGF7K-ZGDWF-QC6LB-GRJE8
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.26.2.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.26.2.0
+Dialog DLL:      DCM.DLL V1.17.2.0
+Target DLL:      STLink\ST-LINKIII-KEIL_SWO.dll V3.0.5.0
+Dialog DLL:      TCM.DLL V1.36.1.0
+ 
+<h2>Project:</h2>
+D:\github\ble_dev\TencentOS-tiny\board\TencentOS_tiny_EVB_MX_Plus\KEIL\qcloud_iot_hub_sdk_coap\TencentOS_tiny.uvprojx
+Project File Date:  11/14/2019
+
+<h2>Output:</h2>
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'TencentOS_tiny'
+compiling HAL_DTLS_mbedtls.c...
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\include\exports\qcloud_iot_export_log.h(94): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Level();
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\include\exports\qcloud_iot_export_log.h(108): warning:  #1295-D: Deprecated declaration IOT_Log_Get_Upload_Level - give arg types
+  LOG_LEVEL IOT_Log_Get_Upload_Level();
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\include\exports\qcloud_iot_export_system.h(38): warning:  #1-D: last line of file ends without a newline
+  #endif /* QCLOUD_IOT_EXPORT_COAP_H_ */
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\include\exports\qcloud_iot_export_dynreg.h(40): warning:  #1-D: last line of file ends without a newline
+  #endif //QLCOUD_IOT_EXPORT_DYNREG_H_
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\platform\tls\mbedtls\HAL_DTLS_mbedtls.c(409): warning:  #1-D: last line of file ends without a newline
+  #endif
+..\..\..\..\components\connectivity\qcloud-iot-hub-sdk-3.1.2\3rdparty\platform\tls\mbedtls\HAL_DTLS_mbedtls.c: 5 warnings, 0 errors
+linking...
+Program Size: Code=132676 RO-data=15568 RW-data=552 ZI-data=54384  
+FromELF: creating hex file...
+".\obj\TencentOS_tiny.axf" - 0 Error(s), 5 Warning(s).
+
+<h2>Software Packages used:</h2>
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
+                ARM.CMSIS.5.6.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.3.0
+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32L4xx_DFP.2.0.0.pack
+                Keil.STM32L4xx_DFP.2.0.0
+                STMicroelectronics STM32L4 Series Device Support, Drivers and Examples
+
+<h2>Collection of Component include folders:</h2>
+  .\RTE\_TencentOS_tiny
+  C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.6.0\CMSIS\Core\Include
+  C:\Keil_v5\ARM\PACK\Keil\STM32L4xx_DFP\2.0.0\Drivers\CMSIS\Device\ST\STM32L4xx\Include
+
+<h2>Collection of Component Files used:</h2>
+
+   * Component: ARM::CMSIS:CORE:5.3.0
+Build Time Elapsed:  00:00:03
+</pre>
+</body>
+</html>

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_coap/obj/TencentOS_tiny.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_mqtt/DebugConfig/TencentOS_tiny_STM32L431RCTx.dbgconf

+// File: STM32L43x_44x_45x_46x.dbgconf
+// Version: 1.0.0
+// Note: refer to STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx Reference manual (RM0394)
+//       refer to STM32L431xx, STM32L432xx, STM32L433xx, STM32L442xx, STM32L443xx, STM32L451xx, STM32L452xx, STM32L462xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o0.2>    DBG_STANDBY
+//     <i> Debug Standby mode
+//     <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
+//     <i> 1: (FCLK=On, HCLK=On) The digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active
+//   <o0.1>    DBG_STOP
+//     <i> Debug Stop mode
+//     <i> 0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). 
+//     <i> 1: (FCLK=On, HCLK=On) When entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode.
+//   <o0.0>    DBG_SLEEP
+//     <i> Debug Sleep mode
+//     <i> 0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled.
+//     <i> 1: (FCLK=On, HCLK=On) When entering Sleep mode, HCLK is fed by the same clock that is provided to FCLK (system clock as previously configured by the software).
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//   <o0.31>    DBG_LPTIM1_STOP
+//     <i> LPTIM1 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM1 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM1 is stopped when the core is halted
+//   <o0.25>    DBG_CAN_STOP
+//     <i> bxCAN1 stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The bxCAN1 receive registers are frozen
+//   <o0.23>    DBG_I2C3_STOP
+//     <i> I2C3 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C3 SMBus timeout is frozen
+//   <o0.22>    DBG_I2C2_STOP
+//     <i> I2C2 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C2 SMBus timeout is frozen
+//   <o0.21>    DBG_I2C1_STOP
+//     <i> I2C1 SMBUS timeout counter stopped when core is halted
+//     <i> 0: Same behavior as in normal mode
+//     <i> 1: The I2C1 SMBus timeout is frozen
+//   <o0.12>    DBG_IWDG_STOP
+//     <i> Independent watchdog counter stopped when core is halted
+//     <i> 0: The independent watchdog counter clock continues even if the core is halted
+//     <i> 1: The independent watchdog counter clock is stopped when the core is halted
+//   <o0.11>    DBG_WWDG_STOP
+//     <i> Window watchdog counter stopped when core is halted
+//     <i> 0: The window watchdog counter clock continues even if the core is halted
+//     <i> 1: The window watchdog counter clock is stopped when the core is halted
+//   <o0.10>    DBG_RTC_STOP
+//     <i> RTC counter stopped when core is halted
+//     <i> 0: The clock of the RTC counter is fed even if the core is halted
+//     <i> 1: The clock of the RTC counter is stopped when the core is halted
+//   <o0.5>    DBG_TIM7_STOP
+//     <i> TIM7 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM7 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM7 is stopped when the core is halted
+//   <o0.4>    DBG_TIM6_STOP
+//     <i> TIM6 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM6 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM6 is stopped when the core is halted
+//   <o0.0>    DBG_TIM2_STOP
+//     <i> TIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of TIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of TIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//   <o0.5>    DBG_LPTIM2_STOP
+//     <i> LPTIM2 counter stopped when core is halted
+//     <i> 0: The counter clock of LPTIM2 is fed even if the core is halted
+//     <i> 1: The counter clock of LPTIM2 is stopped when the core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//   <o0.17>    DBG_TIM16_STOP
+//     <i> TIM16 counter stopped when core is halted
+//     <i> 0: The clock of the TIM16 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM16 counter is stopped when the core is halted
+//   <o0.16>    DBG_TIM15_STOP
+//     <i> TIM15 counter stopped when core is halted
+//     <i> 0: The clock of the TIM15 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM15 counter is stopped when the core is halted
+//   <o0.11>    DBG_TIM1_STOP
+//     <i> TIM1 counter stopped when core is halted
+//     <i> 0: The clock of the TIM1 counter is fed even if the core is halted
+//     <i> 1: The clock of the TIM1 counter is stopped when the core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+// </h>
+
+// <<< end of configuration section >>>
\ No newline at end of file

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_mqtt/EventRecorderStub.scvd

+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

board/TencentOS_tiny_EVB_MX_Plus/KEIL/qcloud_iot_hub_sdk_mqtt/RTE/_TencentOS_tiny/RTE_Components.h

+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'TencentOS_tiny' 
+ * Target:  'TencentOS_tiny' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32l4xx.h"
+
+
+#endif /* RTE_COMPONENTS_H */