[BSP] tm4c129x:

1. Add ETH MAC driver using DMA for Tx and Rx lwip pBuf.
2. Modify the tivaware emac library to fix the bug that PHY read is not stable when sysclk is 120MHz
3. In PHY IRQ handler, insert a dummy reading (REG_BMSR) before read PHY_STS to force update STS register.

bsp/lm4f232/rtconfig.h

@@ -93,7 +93,7 @@
 #define DFS_FD_MAX					4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
-/* #define RT_USING_LWIP */
+#define RT_USING_LWIP
 /* LwIP uses RT-Thread Memory Management */
 #define RT_LWIP_USING_RT_MEM
 /* Enable ICMP protocol*/

bsp/tm4c129x/applications/application.c

@@ -16,6 +16,9 @@
 #include <board.h>
 #include <components.h>
 
+#ifdef RT_USING_LWIP
+#include "drv_eth.h"
+#endif
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
@@ -24,6 +27,9 @@ void rt_init_thread_entry(void *parameter)
 #ifdef RT_USING_FINSH
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+#ifdef RT_USING_LWIP
+    rt_hw_tiva_eth_init();
+#endif
 }
 
 int rt_application_init(void)

bsp/tm4c129x/applications/board.c

@@ -92,7 +92,7 @@ void rt_hw_board_init()
     
     /*init uart device*/		
     rt_hw_uart_init();
-		//redirect RTT stdio to CONSOLE device
+    //redirect RTT stdio to CONSOLE device
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
     //
     // Enable interrupts to the processor.

bsp/tm4c129x/drivers/drv_eth.h

+/*
+ * File      : drv_eth.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2014-07-25     ArdaFu       Port to TM4C129X
+ */
+ 
+#ifndef __TIVA_ETH_H__
+#define __TIVA_ETH_H__
+
+rt_err_t rt_hw_tiva_eth_init(void);
+
+#endif

bsp/tm4c129x/libraries/driverlib/emac.c

@@ -2917,6 +2917,7 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr)
     //
     HWREG(ui32Base + EMAC_O_MIIADDR) =
         ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) |
+					EMAC_MIIADDR_CR_100_150 |
          (ui8RegAddr << EMAC_MIIADDR_MII_S) |
          (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB);