未验证 提交 0af3f746 编写于 作者: J Jiawei Lin 提交者: GitHub

Add IDE support into Makefile and README (#1470)

上级 fac0ab56
......@@ -50,7 +50,7 @@ TIME_CMD = time -a -o $(TIMELOG)
.DEFAULT_GOAL = verilog
help:
mill XiangShan.test.runMain $(SIMTOP) --help
mill -i XiangShan.test.runMain $(SIMTOP) --help
$(TOP_V): $(SCALA_FILE)
mkdir -p $(@D)
......@@ -106,6 +106,9 @@ bump:
bsp:
mill -i mill.bsp.BSP/install
idea:
mill -i mill.scalalib.GenIdea/idea
# verilator simulation
emu:
$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
......
......@@ -55,6 +55,17 @@ Some of the key directories are shown below.
└── xstransforms # some useful firrtl transforms
```
## IDE Support
### bsp
```
make bsp
```
### IDEA
```
make idea
```
## Generate Verilog
......
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