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提交 222e17e5 编写于 作者: L linjiawei
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rewrite core with diplomacy

上级 956965db
隐藏空白更改
内联 并排
Showing with 176 addition and 160 deletion
src/main/scala/system/SoC.scala
浏览文件 @ 222e17e5
......@@ -38,7 +38,7 @@ class DummyCore()(implicit p: Parameters) extends LazyModule {
class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
private val xsCore = LazyModule(new DummyCore())
private val xsCore = LazyModule(new XSCore())
// only mem and extDev visible externally
val mem = xsCore.mem
......
src/main/scala/xiangshan/XSCore.scala
浏览文件 @ 222e17e5
......@@ -2,7 +2,6 @@ package xiangshan
import chisel3._
import chisel3.util._
import bus.simplebus._
import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
import top.Parameters
import xiangshan.backend._
......@@ -11,7 +10,9 @@ import xiangshan.backend.exu.ExuParameters
import xiangshan.frontend._
import xiangshan.mem._
import xiangshan.cache.{DCache, DCacheParameters, ICacheParameters, Uncache}
import bus.tilelink.{TLArbiter, TLCached, TLMasterUtilities, TLParameters}
import chipsalliance.rocketchip.config
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLBundleParameters, TLClientNode, TLIdentityNode}
import utils._
case class XSCoreParameters
......@@ -149,12 +150,6 @@ trait HasXSParameter {
val RefillSize = core.RefillSize
val l1BusDataWidth = 64
val l1BusParams = TLParameters(
addressBits = PAddrBits,
dataBits = l1BusDataWidth,
sourceBits = 3,
sinkBits = 3
)
val icacheParameters = ICacheParameters(
)
......@@ -162,12 +157,11 @@ trait HasXSParameter {
val LRSCCycles = 16
val dcacheParameters = DCacheParameters(
tagECC = Some("secded"),
dataECC = Some("secded"),
busParams = l1BusParams
dataECC = Some("secded")
)
}
trait HasXSLog { this: Module =>
trait HasXSLog { this: RawModule =>
implicit val moduleName: String = this.name
}
......@@ -210,40 +204,27 @@ object AddressSpace extends HasXSParameter {
}
class TLReqProducer extends XSModule {
val io = IO(new TLCached(l1BusParams))
io <> DontCare
class XSCore()(implicit p: config.Parameters) extends LazyModule {
val addr = RegInit("h80000000".U)
addr := addr + 4.U
val (legal, bundle) = TLMasterUtilities.Get(io.params, 0.U, addr, 3.U)
io.a.bits := bundle
io.a.valid := true.B
assert(legal)
io.d.ready := true.B
when(io.a.fire()){
io.a.bits.dump()
}
when(io.d.fire()){
io.d.bits.dump()
}
}
val dcache = LazyModule(new DCache())
val uncache = LazyModule(new Uncache())
class XSCore extends XSModule {
val io = IO(new Bundle {
val mem = new TLCached(l1BusParams)
val mmio = new TLCached(l1BusParams)
})
// TODO: crossbar Icache/Dcache/PTW here
val mem = dcache.clientNode
val mmio = uncache.clientNode
// val fakecache = Module(new TLReqProducer)
// io.mem <> fakecache.io
lazy val module = new XSCoreImp(this)
}
class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) with HasXSParameter {
val front = Module(new Frontend)
val backend = Module(new Backend)
val mem = Module(new Memend)
val dcache = Module(new DCache)
val uncache = Module(new Uncache)
val dcache = outer.dcache.module
val uncache = outer.uncache.module
front.io.backend <> backend.io.frontend
mem.io.backend <> backend.io.mem
......@@ -252,10 +233,6 @@ class XSCore extends XSModule {
dcache.io.lsu.store <> mem.io.sbufferToDcache
uncache.io.lsroq <> mem.io.uncache
io.mmio <> uncache.io.bus
io.mem <> dcache.io.bus
backend.io.memMMU.imem <> DontCare
backend.io.memMMU.dmem <> DontCare
}
src/main/scala/xiangshan/cache/L1Cache.scala
浏览文件 @ 222e17e5
......@@ -4,8 +4,7 @@ package xiangshan.cache
import chisel3._
import chisel3.util._
import xiangshan.{HasXSParameter, XSModule, XSBundle}
import xiangshan.{HasXSParameter, XSBundle, XSModule}
// this file contains common building blocks that can be shared by ICache and DCache
// this is the common parameter base for L1 ICache and L1 DCache
......
src/main/scala/xiangshan/cache/dcache.scala
浏览文件 @ 222e17e5
......@@ -2,16 +2,17 @@ package xiangshan.cache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
import utils.{Code, RandomReplacement, XSDebug}
import utils.{XSDebug, Code, RandomReplacement}
import bus.tilelink.{TLParameters, ClientMetadata}
import scala.math.max
// DCache specific parameters
// L1 DCache is 64set, 8way-associative, with 64byte block, a total of 32KB
// It's a virtually indexed, physically tagged cache.
case class DCacheParameters(
case class DCacheParameters
(
nSets: Int = 64,
nWays: Int = 8,
rowBits: Int = 64,
......@@ -27,8 +28,8 @@ case class DCacheParameters(
nSDQ: Int = 17,
nRPQ: Int = 16,
nMMIOs: Int = 1,
blockBytes: Int = 64,
busParams: TLParameters) extends L1CacheParameters {
blockBytes: Int = 64
) extends L1CacheParameters {
def tagCode: Code = Code.fromString(tagECC)
def dataCode: Code = Code.fromString(dataECC)
......@@ -54,9 +55,9 @@ trait HasDCacheParameters extends HasL1CacheParameters {
def offsetlsb = wordOffBits
def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits)
def get_tag(addr: UInt) = addr >> untagBits
def get_tag(addr: UInt) = (addr >> untagBits).asUInt()
def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits)
def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits
def get_block_addr(addr: UInt) = ((addr >> blockOffBits) << blockOffBits).asUInt()
def rowWords = rowBits/wordBits
def doNarrowRead = DataBits * nWays % rowBits == 0
......@@ -200,9 +201,9 @@ class DuplicatedDataArray extends AbstractDataArray
{
// write is always ready
io.write.ready := true.B
val waddr = io.write.bits.addr >> blockOffBits
val waddr = (io.write.bits.addr >> blockOffBits).asUInt()
for (j <- 0 until LoadPipelineWidth) {
val raddr = io.read(j).bits.addr >> blockOffBits
val raddr = (io.read(j).bits.addr >> blockOffBits).asUInt()
// raddr === waddr is undefined behavior!
// block read in this case
io.read(j).ready := !io.write.valid || raddr =/= waddr
......
src/main/scala/xiangshan/cache/dcacheWrapper.scala
浏览文件 @ 222e17e5
package xiangshan.cache
import chipsalliance.rocketchip.config.Parameters
import chisel3._
import chisel3.util._
import utils.XSDebug
import bus.tilelink._
import xiangshan.{MicroOp}
import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
import freechips.rocketchip.tilelink.{TLClientNode, TLClientParameters, TLMasterParameters, TLMasterPortParameters}
import xiangshan.MicroOp
// Meta data for dcache requests
// anything that should go with reqs and resps goes here
......@@ -76,12 +76,30 @@ class DCacheToLsuIO extends DCacheBundle {
class DCacheIO extends DCacheBundle {
val lsu = new DCacheToLsuIO
val bus = new TLCached(cfg.busParams)
}
class DCache extends DCacheModule {
class DCache()(implicit p: Parameters) extends LazyModule with HasDCacheParameters {
val clientParameters = TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "dcache",
sourceId = IdRange(0, cfg.nMissEntries+1)
))
)
val clientNode = TLClientNode(Seq(clientParameters))
lazy val module = new DCacheImp(this)
}
class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParameters {
val io = IO(new DCacheIO)
val (bus, edge) = outer.clientNode.out.head
//----------------------------------------
// core data structures
val dataArray = Module(new DuplicatedDataArray)
......@@ -94,8 +112,8 @@ class DCache extends DCacheModule {
val stu = Module(new StorePipe)
val loadMissQueue = Module(new LoadMissQueue)
val storeMissQueue = Module(new StoreMissQueue)
val missQueue = Module(new MissQueue)
val wb = Module(new WritebackUnit)
val missQueue = Module(new MissQueue(edge))
val wb = Module(new WritebackUnit(edge))
//----------------------------------------
......@@ -297,35 +315,35 @@ class DCache extends DCacheModule {
missFinish <> missFinishArb.io.out
// tilelink stuff
io.bus.a <> missQueue.io.mem_acquire
io.bus.e <> missQueue.io.mem_finish
bus.a <> missQueue.io.mem_acquire
bus.e <> missQueue.io.mem_finish
when (io.bus.d.bits.source === cfg.nMissEntries.U) {
when (bus.d.bits.source === cfg.nMissEntries.U) {
// This should be ReleaseAck
io.bus.d.ready := true.B
bus.d.ready := true.B
missQueue.io.mem_grant.valid := false.B
missQueue.io.mem_grant.bits := DontCare
} .otherwise {
// This should be GrantData
missQueue.io.mem_grant <> io.bus.d
missQueue.io.mem_grant <> bus.d
}
//----------------------------------------
// prober
io.bus.b.ready := false.B
bus.b.ready := false.B
//----------------------------------------
// wb
// 0 goes to prober, 1 goes to missQueue evictions
val wbArb = Module(new Arbiter(new WritebackReq, 2))
val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle.sourceBits), 2))
wbArb.io.in(0).valid := false.B
wbArb.io.in(0).bits := DontCare
wbArb.io.in(1) <> missQueue.io.wb_req
wb.io.req <> wbArb.io.out
missQueue.io.wb_resp := wb.io.resp
io.bus.c <> wb.io.release
wb.io.mem_grant := io.bus.d.fire() && io.bus.d.bits.source === cfg.nMissEntries.U
bus.c <> wb.io.release
wb.io.mem_grant := bus.d.fire() && bus.d.bits.source === cfg.nMissEntries.U
// synchronization stuff
def block_load(addr: UInt) = {
......
src/main/scala/xiangshan/cache/missQueue.scala
浏览文件 @ 222e17e5
......@@ -2,9 +2,8 @@ package xiangshan.cache
import chisel3._
import chisel3.util._
import freechips.rocketchip.tilelink._
import utils.XSDebug
import bus.tilelink._
class MissReq extends DCacheBundle
{
......@@ -27,7 +26,7 @@ class MissFinish extends DCacheBundle
// One miss entry deals with one missed block
class MissEntry extends DCacheModule
class MissEntry(edge: TLEdgeOut) extends DCacheModule
{
val io = IO(new Bundle {
// MSHR ID
......@@ -41,16 +40,16 @@ class MissEntry extends DCacheModule
val block_idx = Output(Valid(UInt()))
val block_addr = Output(Valid(UInt()))
val mem_acquire = DecoupledIO(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(DecoupledIO(new TLBundleD(cfg.busParams)))
val mem_finish = DecoupledIO(new TLBundleE(cfg.busParams))
val mem_acquire = DecoupledIO(new TLBundleA(edge.bundle))
val mem_grant = Flipped(DecoupledIO(new TLBundleD(edge.bundle)))
val mem_finish = DecoupledIO(new TLBundleE(edge.bundle))
val meta_read = DecoupledIO(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
val meta_write = DecoupledIO(new L1MetaWriteReq)
val refill = DecoupledIO(new L1DataWriteReq)
val wb_req = DecoupledIO(new WritebackReq)
val wb_req = DecoupledIO(new WritebackReq(edge.bundle.sourceBits))
val wb_resp = Input(Bool())
})
......@@ -84,9 +83,9 @@ class MissEntry extends DCacheModule
val grow_param = new_coh.onAccess(req.cmd)._2
val coh_on_grant = new_coh.onGrant(req.cmd, io.mem_grant.bits.param)
val (_, _, refill_done, refill_address_inc) = TLUtilities.addr_inc(io.mem_grant)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val grantack = Reg(Valid(new TLBundleE(cfg.busParams)))
val grantack = Reg(Valid(new TLBundleE(edge.bundle)))
val refill_ctr = Reg(UInt(log2Up(cacheDataBeats).W))
val should_refill_data = Reg(Bool())
......@@ -240,10 +239,10 @@ class MissEntry extends DCacheModule
when (state === s_refill_req) {
io.mem_acquire.valid := true.B
// TODO: Use AcquirePerm if just doing permissions acquire
io.mem_acquire.bits := TLMasterUtilities.AcquireBlock(
params = cfg.busParams,
// TODO: review this
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = io.id,
toAddress = Cat(req_tag, req_idx) << blockOffBits,
toAddress = (Cat(req_tag, req_idx) << blockOffBits).asUInt(),
lgSize = (log2Up(cfg.blockBytes)).U,
growPermissions = grow_param)._2
when (io.mem_acquire.fire()) {
......@@ -255,7 +254,7 @@ class MissEntry extends DCacheModule
when (state === s_refill_resp) {
io.mem_grant.ready := true.B
when (TLUtilities.hasData(io.mem_grant.bits)) {
when (edge.hasData(io.mem_grant.bits)) {
when (io.mem_grant.fire()) {
should_refill_data := true.B
refill_ctr := refill_ctr + 1.U
......@@ -267,8 +266,8 @@ class MissEntry extends DCacheModule
}
when (refill_done) {
grantack.valid := TLUtilities.isRequest(io.mem_grant.bits)
grantack.bits := TLMasterUtilities.GrantAck(io.mem_grant.bits)
grantack.valid := edge.isRequest(io.mem_grant.bits)
grantack.bits := edge.GrantAck(io.mem_grant.bits)
new_coh := coh_on_grant
state := s_mem_finish
......@@ -345,23 +344,23 @@ class MissEntry extends DCacheModule
}
class MissQueue extends DCacheModule
class MissQueue(edge: TLEdgeOut) extends DCacheModule
{
val io = IO(new Bundle {
val req = Flipped(DecoupledIO(new MissReq))
val resp = ValidIO(new MissResp)
val finish = Flipped(DecoupledIO(new MissFinish))
val mem_acquire = Decoupled(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(Decoupled(new TLBundleD(cfg.busParams)))
val mem_finish = Decoupled(new TLBundleE(cfg.busParams))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Vec(nWays, new L1Metadata))
val meta_write = Decoupled(new L1MetaWriteReq)
val refill = Decoupled(new L1DataWriteReq)
val wb_req = Decoupled(new WritebackReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle.sourceBits))
val wb_resp = Input(Bool())
val inflight_req_idxes = Output(Vec(cfg.nMissEntries, Valid(UInt())))
......@@ -372,7 +371,7 @@ class MissQueue extends DCacheModule
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, cfg.nMissEntries))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, cfg.nMissEntries))
val refill_arb = Module(new Arbiter(new L1DataWriteReq, cfg.nMissEntries))
val wb_req_arb = Module(new Arbiter(new WritebackReq, cfg.nMissEntries))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle.sourceBits), cfg.nMissEntries))
// assign default values to output signals
io.finish.ready := false.B
......@@ -382,7 +381,7 @@ class MissQueue extends DCacheModule
val req_ready = WireInit(false.B)
val entries = (0 until cfg.nMissEntries) map { i =>
val entry = Module(new MissEntry)
val entry = Module(new MissEntry(edge))
entry.io.id := i.U(log2Up(cfg.nMissEntries).W)
......@@ -436,8 +435,8 @@ class MissQueue extends DCacheModule
io.refill <> refill_arb.io.out
io.wb_req <> wb_req_arb.io.out
TLArbiter.lowestFromSeq(io.mem_acquire, entries.map(_.io.mem_acquire))
TLArbiter.lowestFromSeq(io.mem_finish, entries.map(_.io.mem_finish))
TLArbiter.lowestFromSeq(edge, io.mem_acquire, entries.map(_.io.mem_acquire))
TLArbiter.lowestFromSeq(edge, io.mem_finish, entries.map(_.io.mem_finish))
// print all input/output requests for debug purpose
......@@ -470,16 +469,17 @@ class MissQueue extends DCacheModule
io.wb_req.bits.way_en, io.wb_req.bits.voluntary)
// print tilelink messages
// TODO: impl TLBundle.dump
when (io.mem_acquire.fire()) {
XSDebug("mem_acquire ")
io.mem_acquire.bits.dump
// io.mem_acquire.bits.dump
}
when (io.mem_grant.fire()) {
XSDebug("mem_grant ")
io.mem_grant.bits.dump
// io.mem_grant.bits.dump
}
when (io.mem_finish.fire()) {
XSDebug("mem_finish ")
io.mem_finish.bits.dump
// io.mem_finish.bits.dump
}
}
src/main/scala/xiangshan/cache/uncache.scala
浏览文件 @ 222e17e5
......@@ -2,13 +2,14 @@ package xiangshan.cache
import chisel3._
import chisel3.util._
import utils.XSDebug
import bus.tilelink._
import xiangshan.{MicroOp, Redirect, NeedImpl}
import chipsalliance.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
import freechips.rocketchip.tilelink.{TLArbiter, TLBundleA, TLBundleD, TLClientNode, TLEdgeOut, TLMasterParameters, TLMasterPortParameters}
import xiangshan.{HasXSLog, MicroOp, NeedImpl, Redirect}
// One miss entry deals with one mmio request
class MMIOEntry extends DCacheModule
class MMIOEntry(edge: TLEdgeOut) extends DCacheModule
{
val io = IO(new Bundle {
// MSHR ID
......@@ -18,8 +19,8 @@ class MMIOEntry extends DCacheModule
val req = Flipped(DecoupledIO(new DCacheWordReq ))
val resp = DecoupledIO(new DCacheResp)
val mem_acquire = DecoupledIO(new TLBundleA(cfg.busParams))
val mem_grant = Flipped(DecoupledIO(new TLBundleD(cfg.busParams)))
val mem_acquire = DecoupledIO(new TLBundleA(edge.bundle))
val mem_grant = Flipped(DecoupledIO(new TLBundleD(edge.bundle)))
})
val s_invalid :: s_refill_req :: s_refill_resp :: s_send_resp :: Nil = Enum(4)
......@@ -56,19 +57,19 @@ class MMIOEntry extends DCacheModule
// --------------------------------------------
// refill
// access 64bit data, addr are 64bit aligned
val load = TLMasterUtilities.Get(
params = cfg.busParams,
val load = edge.Get(
fromSource = io.id,
toAddress = req.addr,
lgSize = (log2Up(DataBits)).U)._2
lgSize = log2Up(DataBits).U
)._2
val store = TLMasterUtilities.Put(
params = cfg.busParams,
val store = edge.Put(
fromSource = io.id,
toAddress = req.addr,
lgSize = (log2Up(DataBits)).U,
data = req.data,
mask = req.mask)._2
mask = req.mask
)._2
when (state === s_refill_req) {
io.mem_acquire.valid := true.B
......@@ -79,7 +80,7 @@ class MMIOEntry extends DCacheModule
}
}
val (_, _, refill_done, _) = TLUtilities.addr_inc(io.mem_grant)
val (_, _, refill_done, _) = edge.addr_inc(io.mem_grant)
when (state === s_refill_resp) {
io.mem_grant.ready := true.B
......@@ -108,34 +109,54 @@ class MMIOEntry extends DCacheModule
class UncacheIO extends DCacheBundle {
val lsroq = Flipped(new DCacheLoadIO)
val bus = new TLCached(l1BusParams)
}
// convert DCacheIO to TileLink
// for Now, we only deal with TL-UL
class Uncache extends DCacheModule {
class Uncache()(implicit p: Parameters) extends LazyModule with HasDCacheParameters {
val clientParameters = TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
"uncache",
sourceId = IdRange(0, cfg.nMMIOEntries)
))
)
val clientNode = TLClientNode(Seq(clientParameters))
lazy val module = new UncacheImp(this)
}
class UncacheImp(outer: Uncache)
extends LazyModuleImp(outer)
with HasDCacheParameters
with HasXSLog
{
val io = IO(new UncacheIO)
val (bus, edge) = outer.clientNode.out.head
val resp_arb = Module(new Arbiter(new DCacheResp, cfg.nMMIOEntries))
val req = io.lsroq.req
val resp = io.lsroq.resp
val mem_acquire = io.bus.a
val mem_grant = io.bus.d
val mem_acquire = bus.a
val mem_grant = bus.d
val entry_alloc_idx = Wire(UInt())
val req_ready = WireInit(false.B)
// assign default values to output signals
io.bus.b.ready := false.B
io.bus.c.valid := false.B
io.bus.c.bits := DontCare
io.bus.d.ready := false.B
io.bus.e.valid := false.B
io.bus.e.bits := DontCare
bus.b.ready := false.B
bus.c.valid := false.B
bus.c.bits := DontCare
bus.d.ready := false.B
bus.e.valid := false.B
bus.e.bits := DontCare
val entries = (0 until cfg.nMMIOEntries) map { i =>
val entry = Module(new MMIOEntry)
val entry = Module(new MMIOEntry(edge))
entry.io.id := i.U(log2Up(cfg.nMMIOEntries).W)
......@@ -161,7 +182,7 @@ class Uncache extends DCacheModule {
req.ready := req_ready
resp <> resp_arb.io.out
TLArbiter.lowestFromSeq(mem_acquire, entries.map(_.io.mem_acquire))
TLArbiter.lowestFromSeq(edge, mem_acquire, entries.map(_.io.mem_acquire))
// print all input/output requests for debug purpose
......@@ -172,12 +193,13 @@ class Uncache extends DCacheModule {
XSDebug(resp.fire(), "data: %x\n", req.bits.data)
// print tilelink messages
// TODO: add dump info
when (mem_acquire.fire()) {
XSDebug("mem_acquire ")
mem_acquire.bits.dump
XSDebug("mem_acquire \n")
// mem_acquire.bits.dump
}
when (mem_grant.fire()) {
XSDebug("mem_grant ")
mem_grant.bits.dump
XSDebug("mem_grant \n")
// mem_grant.bits.dump
}
}
src/main/scala/xiangshan/cache/wbu.scala
浏览文件 @ 222e17e5
......@@ -2,38 +2,37 @@ package xiangshan.cache
import chisel3._
import chisel3.util._
import chisel3.util.experimental.BoringUtils
import utils.XSDebug
import bus.tilelink._
import freechips.rocketchip.tilelink.{TLBundleC, TLEdgeOut, TLPermissions}
class WritebackReq extends DCacheBundle {
class WritebackReq(sourceBits: Int) extends DCacheBundle {
val tag = Bits(tagBits.W)
val idx = Bits(idxBits.W)
// TODO: make it configurable
val source = UInt(cfg.busParams.sourceBits.W)
val source = UInt(sourceBits.W)
val param = UInt(TLPermissions.cWidth.W)
val way_en = Bits(nWays.W)
val voluntary = Bool()
override def cloneType: WritebackReq.this.type = new WritebackReq(sourceBits).asInstanceOf[this.type]
}
class WritebackUnit extends DCacheModule {
class WritebackUnit(edge: TLEdgeOut) extends DCacheModule {
val io = IO(new Bundle {
val req = Flipped(DecoupledIO(new WritebackReq()))
val req = Flipped(DecoupledIO(new WritebackReq(edge.bundle.sourceBits)))
val resp = Output(Bool())
val data_req = DecoupledIO(new L1DataReadReq)
val data_resp = Input(Vec(nWays, Vec(refillCycles, Bits(encRowBits.W))))
val release = DecoupledIO(new TLBundleC(cfg.busParams))
val release = DecoupledIO(new TLBundleC(edge.bundle))
val mem_grant = Input(Bool())
})
val req = Reg(new WritebackReq())
val req = Reg(new WritebackReq(edge.bundle.sourceBits))
val s_invalid :: s_data_read_req :: s_data_read_resp_1 :: s_data_read_resp_2 :: s_active :: s_grant :: Nil = Enum(6)
val state = RegInit(s_invalid)
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))
val (_, last_beat, all_beats_done, beat_count) = TLUtilities.count(io.release)
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)
val wb_buffer = Reg(Vec(refillCycles, UInt(rowBits.W)))
val acked = RegInit(false.B)
......@@ -84,23 +83,24 @@ class WritebackUnit extends DCacheModule {
}
// release
val r_address = Cat(req.tag, req.idx) << blockOffBits
val r_address = (Cat(req.tag, req.idx) << blockOffBits).asUInt()
val id = cfg.nMissEntries
val probeResponse = TLMasterUtilities.ProbeAck(
params = cfg.busParams,
fromSource = id.U,
toAddress = r_address,
lgSize = log2Ceil(cfg.blockBytes).U,
reportPermissions = req.param,
data = wb_buffer(data_req_cnt))
val voluntaryRelease = TLMasterUtilities.Release(
params = cfg.busParams,
fromSource = id.U,
toAddress = r_address,
lgSize = log2Ceil(cfg.blockBytes).U,
shrinkPermissions = req.param,
data = wb_buffer(data_req_cnt))._2
val probeResponse = edge.ProbeAck(
fromSource = id.U,
toAddress = r_address,
lgSize = log2Ceil(cfg.blockBytes).U,
reportPermissions = req.param,
data = wb_buffer(data_req_cnt)
)
val voluntaryRelease = edge.Release(
fromSource = id.U,
toAddress = r_address,
lgSize = log2Ceil(cfg.blockBytes).U,
shrinkPermissions = req.param,
data = wb_buffer(data_req_cnt)
)._2
when (state === s_active) {
io.release.valid := data_req_cnt < refillCycles.U
......
src/main/scala/xiangshan/mem/Memend.scala
浏览文件 @ 222e17e5
......@@ -116,7 +116,7 @@ class Memend extends XSModule {
val loadUnitToDcacheVec = Vec(exuParameters.LduCnt, new DCacheLoadIO)
val miscToDcache = new DCacheLoadIO
val sbufferToDcache = new DCacheStoreIO
val uncache = new UncacheIO
val uncache = new DCacheLoadIO
})
val loadUnits = (0 until exuParameters.LduCnt).map(_ => Module(new LoadUnit))
......@@ -139,11 +139,10 @@ class Memend extends XSModule {
val lsroqToDcache = Wire(new DCacheLoadIO)
val miscUnitToDcache = Wire(new DCacheLoadIO)
// misc + miss --> arbiter --> miscToDcache
val miscToDcache = Wire(new DCacheLoadIO)
val miscToDcache = io.miscToDcache
// connect dcache ports
io.loadUnitToDcacheVec <> loadUnitToDcacheVec
io.miscToDcache <> miscToDcache
io.sbufferToDcache <> sbufferToDcache
io.uncache <> lsroqToUncache
......@@ -198,9 +197,9 @@ class Memend extends XSModule {
miscUnit.io.dcache <> miscUnitToDcache
assert(!(lsroqToDcache.req.valid && miscUnitToDcache.req.valid))
val memReqArb = new Arbiter(miscToDcache.req, 2)
memReqArb.io.in(0) := lsroqToDcache.req
memReqArb.io.in(1) := miscUnitToDcache.req
val memReqArb = Module(new Arbiter(miscToDcache.req.bits.cloneType, 2))
memReqArb.io.in(0) <> lsroqToDcache.req
memReqArb.io.in(1) <> miscUnitToDcache.req
miscToDcache.req <> memReqArb.io.out
......
src/test/scala/top/XSSim.scala
浏览文件 @ 222e17e5
......@@ -9,7 +9,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
import device._
import freechips.rocketchip.amba.axi4.AXI4UserYanker
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLBuffer, TLFuzzer, TLToAXI4}
import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter, TLFuzzer, TLToAXI4, TLXbar}
import xiangshan._
import utils._
import firrtl.stage.RunFirrtlTransformAnnotation
......
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