dispatch: don't split int/fp and mem regfile read ports

src/main/scala/xiangshan/backend/Backend.scala

@@ -198,10 +198,10 @@ class Backend extends XSModule
   rename.io.redirect <> redirect
   rename.io.roqCommits <> roq.io.commits
   rename.io.in <> decBuf.io.out
-  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.memIntRf.map(_.addr)
-  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
-  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.memFpRf.map(_.addr)
-  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
+  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
+  rename.io.intPregRdy <> dispatch.io.intPregRdy
+  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
+  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
   rename.io.replayPregReq <> dispatch.io.replayPregReq
   dispatch.io.redirect <> redirect
   dispatch.io.fromRename <> rename.io.out
@@ -219,8 +219,8 @@ class Backend extends XSModule
   dispatch.io.dequeueRoqIndex.bits := Mux(io.mem.oldestStore.valid, io.mem.oldestStore.bits, roq.io.commitRoqIndex.bits)
 
 
-  intRf.io.readPorts <> dispatch.io.readIntRf ++ dispatch.io.memIntRf
-  fpRf.io.readPorts <> dispatch.io.readFpRf ++ dispatch.io.memFpRf
+  intRf.io.readPorts <> dispatch.io.readIntRf
+  fpRf.io.readPorts <> dispatch.io.readFpRf
 
   io.mem.redirect <> redirect
 

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -48,16 +48,11 @@ class Dispatch
     val lsIdxs = Input(Vec(RenameWidth, new LSIdx))
     val dequeueRoqIndex = Input(Valid(new RoqPtr))
     // read regfile
-    val readIntRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
-    val readFpRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort))
+    val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
+    val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort))
     // read reg status (busy/ready)
-    val intPregRdy = Vec(NRIntReadPorts - NRMemReadPorts, Input(Bool()))
-    val fpPregRdy = Vec(NRFpReadPorts - exuParameters.StuCnt, Input(Bool()))
-    // load + store reg status (busy/ready)
-    val memIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort))
-    val memFpRf = Vec(exuParameters.StuCnt, Flipped(new RfReadPort))
-    val intMemRegRdy = Vec(NRMemReadPorts, Input(Bool()))
-    val fpMemRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
+    val intPregRdy = Vec(NRIntReadPorts, Input(Bool()))
+    val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
     // replay: set preg status to not ready
     val replayPregReq = Output(Vec(ReplayWidth, new ReplayPregReq))
     // to reservation stations
@@ -118,34 +113,28 @@ class Dispatch
   // Int dispatch queue to Int reservation stations
   val intDispatch = Module(new Dispatch2Int(jmpCfg, aluCfg, mduCfg))
   intDispatch.io.fromDq <> intDq.io.deq
-  intDispatch.io.readRf <> io.readIntRf
-  intDispatch.io.regRdy := io.intPregRdy
+  intDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i)})
+  intDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.intPregRdy(i)})
   intDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(i)})
   intDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i)})
   intDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i)})
 
-  // TODO: Fp dispatch queue to Fp reservation stations
-  if (exuParameters.FpExuCnt > 0) {
-    val fpDispatch = Module(new Dispatch2Fp(fmacCfg, fmiscCfg))
-    fpDispatch.io.fromDq <> fpDq.io.deq
-    fpDispatch.io.readRf <> io.readFpRf
-    fpDispatch.io.regRdy <> io.fpPregRdy
-    fpDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(i + exuParameters.IntExuCnt)})
-    fpDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i + exuParameters.IntExuCnt)})
-    fpDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i + exuParameters.IntExuCnt)})
-  }
-  else {
-    fpDq.io.deq <> DontCare
-    io.readFpRf <> DontCare
-  }
+  // Fp dispatch queue to Fp reservation stations
+  val fpDispatch = Module(new Dispatch2Fp(fmacCfg, fmiscCfg))
+  fpDispatch.io.fromDq <> fpDq.io.deq
+  fpDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i)})
+  fpDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.fpPregRdy(i)})
+  fpDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(i + exuParameters.IntExuCnt)})
+  fpDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i + exuParameters.IntExuCnt)})
+  fpDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i + exuParameters.IntExuCnt)})
   
   // Load/store dispatch queue to load/store issue queues
   val lsDispatch = Module(new Dispatch2Ls(ldCfg, stCfg))
   lsDispatch.io.fromDq <> lsDq.io.deq
-  lsDispatch.io.readIntRf <> io.memIntRf
-  lsDispatch.io.readFpRf <> io.memFpRf
-  lsDispatch.io.intRegRdy <> io.intMemRegRdy
-  lsDispatch.io.fpRegRdy <> io.fpMemRegRdy
+  lsDispatch.io.readIntRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i + 8)})
+  lsDispatch.io.readFpRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i + 12)})
+  lsDispatch.io.intRegRdy.zipWithIndex.map({case (r, i) => r <> io.intPregRdy(i + 8)})
+  lsDispatch.io.fpRegRdy.zipWithIndex.map({case (r, i) => r <> io.fpPregRdy(i + 12)})
   lsDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
   lsDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
   lsDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})