IFU: add MMIO parameters

src/main/scala/xiangshan/cache/icache.scala

@@ -59,11 +59,13 @@ trait HasFrontEndExceptionNo {
 
 abstract class ICacheBundle extends XSBundle
   with HasICacheParameters
+  with HasInstrMMIOConst
 
 abstract class ICacheModule extends XSModule
   with HasICacheParameters
   with ICacheBase
   with HasFrontEndExceptionNo
+  with HasInstrMMIOConst
 
 abstract class ICacheArray extends XSModule
   with HasICacheParameters

src/main/scala/xiangshan/frontend/IFU.scala

@@ -9,6 +9,13 @@ import xiangshan.cache._
 import chisel3.experimental.chiselName
 import freechips.rocketchip.tile.HasLazyRoCC
 
+trait HasInstrMMIOConst extends HasXSParameter{
+  def mmioBusWidth = 64
+  def mmioBusBytes = mmioBusWidth /8
+  def mmioBeats = FetchWidth * 4 / mmioBusWidth
+  def mmioMask  = VecInit(List.fill(PredictWidth)(true.B)).asUInt
+}
+
 trait HasIFUConst extends HasXSParameter {
   val resetVector = 0x80000000L//TODO: set reset vec
   def align(pc: UInt, bytes: Int): UInt = Cat(pc(VAddrBits-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W))