soc: add peripheral range to dma error device

src/main/scala/system/SoC.scala

@@ -127,7 +127,7 @@ trait HaveSlaveAXI4Port {
   private val errorDevice = LazyModule(new TLError(
     params = DevNullParams(
       // requests to address below memory will be granted with erros
-      address = paddrRange.subtract(getAddressSet("memory") ++ getAddressSet("peripheral")),
+      address = paddrRange.subtract(getAddressSet("memory")),
       maxAtomic = 8,
       maxTransfer = 64),
     beatBytes = L3InnerBusWidth / 8
@@ -193,11 +193,6 @@ trait HaveAXI4MemPort {
     TLCacheCork() :=*
     bankedNode
 
-  // mem_xbar :=
-  //   TLWidthWidget(8) :=
-  //   TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
-  //   peripheralXbar
-
   class MemPortClockDivDomain()(implicit p: Parameters) extends LazyModule {
     val memoryNode = AXI4IdentityNode()
     val rationalNode = TLRationalIdentityNode()