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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
3a474d38
编写于
1月 30, 2021
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
roq: rename RoqExceptionInfo to ExceptionInfo
上级
620026c3
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
11 addition
and
54 deletion
+11
-54
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+5
-0
src/main/scala/xiangshan/backend/CtrlBlock.scala
src/main/scala/xiangshan/backend/CtrlBlock.scala
+2
-2
src/main/scala/xiangshan/backend/IntegerBlock.scala
src/main/scala/xiangshan/backend/IntegerBlock.scala
+1
-2
src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala
src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala
+1
-2
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+1
-2
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+1
-46
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
3a474d38
...
...
@@ -358,6 +358,11 @@ class CSRSpecialIO extends XSBundle {
val
interrupt
=
Output
(
Bool
())
}
class
ExceptionInfo
extends
XSBundle
{
val
uop
=
new
MicroOp
val
isInterrupt
=
Bool
()
}
class
RoqCommitInfo
extends
XSBundle
{
val
ldest
=
UInt
(
5.
W
)
val
rfWen
=
Bool
()
...
...
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @
3a474d38
...
...
@@ -11,7 +11,7 @@ import xiangshan.backend.exu._
import
xiangshan.backend.exu.Exu.exuConfigs
import
xiangshan.backend.ftq.
{
Ftq
,
FtqRead
,
GetPcByFtq
}
import
xiangshan.backend.regfile.RfReadPort
import
xiangshan.backend.roq.
{
Roq
,
RoqCSRIO
,
RoqLsqIO
,
RoqPtr
,
RoqExceptionInfo
}
import
xiangshan.backend.roq.
{
Roq
,
RoqCSRIO
,
RoqLsqIO
,
RoqPtr
}
import
xiangshan.mem.LsqEnqIO
class
CtrlToIntBlockIO
extends
XSBundle
{
...
...
@@ -173,7 +173,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
val
roqio
=
new
Bundle
{
// to int block
val
toCSR
=
new
RoqCSRIO
val
exception
=
ValidIO
(
new
Roq
ExceptionInfo
)
val
exception
=
ValidIO
(
new
ExceptionInfo
)
// to mem block
val
lsq
=
new
RoqLsqIO
}
...
...
src/main/scala/xiangshan/backend/IntegerBlock.scala
浏览文件 @
3a474d38
...
...
@@ -8,7 +8,6 @@ import xiangshan.backend.exu._
import
xiangshan.backend.fu.FenceToSbuffer
import
xiangshan.backend.issue.
{
ReservationStation
}
import
xiangshan.backend.regfile.Regfile
import
xiangshan.backend.roq.RoqExceptionInfo
class
WakeUpBundle
(
numFast
:
Int
,
numSlow
:
Int
)
extends
XSBundle
{
val
fastUops
=
Vec
(
numFast
,
Flipped
(
ValidIO
(
new
MicroOp
)))
...
...
@@ -76,7 +75,7 @@ class IntegerBlock
val
fflags
=
Flipped
(
Valid
(
UInt
(
5.
W
)))
// from roq
val
dirty_fs
=
Input
(
Bool
())
// from roq
val
frm
=
Output
(
UInt
(
3.
W
))
// to float
val
exception
=
Flipped
(
ValidIO
(
new
Roq
ExceptionInfo
))
val
exception
=
Flipped
(
ValidIO
(
new
ExceptionInfo
))
val
trapTarget
=
Output
(
UInt
(
VAddrBits
.
W
))
// to roq
val
isXRet
=
Output
(
Bool
())
val
interrupt
=
Output
(
Bool
())
// to roq
...
...
src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala
浏览文件 @
3a474d38
...
...
@@ -7,7 +7,6 @@ import xiangshan._
import
xiangshan.backend.exu.Exu.jumpExeUnitCfg
import
xiangshan.backend.fu.fpu.IntToFP
import
xiangshan.backend.fu.
{
CSR
,
Fence
,
FenceToSbuffer
,
FunctionUnit
,
Jump
}
import
xiangshan.backend.roq.RoqExceptionInfo
class
JumpExeUnit
extends
Exu
(
jumpExeUnitCfg
)
{
...
...
@@ -15,7 +14,7 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
val
fflags
=
Flipped
(
ValidIO
(
UInt
(
5.
W
)))
val
dirty_fs
=
Input
(
Bool
())
val
frm
=
Output
(
UInt
(
3.
W
))
val
exception
=
Flipped
(
ValidIO
(
new
Roq
ExceptionInfo
))
val
exception
=
Flipped
(
ValidIO
(
new
ExceptionInfo
))
val
trapTarget
=
Output
(
UInt
(
VAddrBits
.
W
))
val
isXRet
=
Output
(
Bool
())
val
interrupt
=
Output
(
Bool
())
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
3a474d38
...
...
@@ -7,7 +7,6 @@ import utils._
import
xiangshan._
import
xiangshan.backend._
import
xiangshan.backend.fu.util._
import
xiangshan.backend.roq.RoqExceptionInfo
object
hartId
extends
(()
=>
Int
)
{
var
x
=
0
...
...
@@ -132,7 +131,7 @@ class CSR extends FunctionUnit with HasCSRConst
// to FPU
val
fpu
=
Flipped
(
new
FpuCsrIO
)
// from rob
val
exception
=
Flipped
(
ValidIO
(
new
Roq
ExceptionInfo
))
val
exception
=
Flipped
(
ValidIO
(
new
ExceptionInfo
))
// to ROB
val
isXRet
=
Output
(
Bool
())
val
trapTarget
=
Output
(
UInt
(
VAddrBits
.
W
))
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
3a474d38
...
...
@@ -166,51 +166,6 @@ class RoqEnqPtrWrapper extends XSModule with HasCircularQueuePtrHelper {
}
// class RoqStateWrapper extends XSModule with HasCircularQueuePtrHelper {
// val io = IO(new Bundle {
// val redirect = ValidIO(new Redirect)
// val raddr = Vec(CommitWidth, Input(UInt(log2Up(numEntries).W)))
// val wen = Vec(RenameWidth, Input(Bool()))
// val waddr = Vec(RenameWidth)
// })
// val valid = Mme(RoqSize, Bool())
// val flagBkup = RegInit(VecInit(List.fill(RoqSize)(false.B)))
// for (i <- 0 until RoqSize) {
// when (reset.asBool || io.redirectOut.valid) {
// valid(i) := false.B
// }.elsewhen (io.redirectOut.valid)
// }
// when (reset.asBool) {
// valid(i)
// }
// // enqueue logic writes 6 valid
// for (i <- 0 until RenameWidth) {
// when (canEnqueue(i) && !io.redirect.valid) {
// valid(enqPtrVec(i).value) := true.B
// }
// }
// // dequeue/walk logic writes 6 valid, dequeue and walk will not happen at the same time
// for (i <- 0 until CommitWidth) {
// when (io.commits.valid(i) && state =/= s_extrawalk) {
// valid(commitReadAddr(i)) := false.B
// }
// }
// // reset: when exception, reset all valid to false
// when (io.redirectOut.valid) {
// for (i <- 0 until RoqSize) {
// valid(i) := false.B
// }
// }
// }
class
RoqExceptionInfo
extends
XSBundle
{
val
uop
=
new
MicroOp
val
isInterrupt
=
Bool
()
}
class
RoqFlushInfo
extends
XSBundle
{
val
ftqIdx
=
new
FtqPtr
val
ftqOffset
=
UInt
(
log2Up
(
PredictWidth
).
W
)
...
...
@@ -221,7 +176,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
val
redirect
=
Input
(
Valid
(
new
Redirect
))
val
enq
=
new
RoqEnqIO
val
flushOut
=
ValidIO
(
new
RoqFlushInfo
)
val
exception
=
ValidIO
(
new
Roq
ExceptionInfo
)
val
exception
=
ValidIO
(
new
ExceptionInfo
)
// exu + brq
val
exeWbResults
=
Vec
(
numWbPorts
,
Flipped
(
ValidIO
(
new
ExuOutput
)))
val
commits
=
new
RoqCommitIO
...
...
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