dispatch: support reservation stations for load/store

src/main/scala/xiangshan/backend/Backend.scala

@@ -161,9 +161,9 @@ class Backend extends XSModule
   rename.io.redirect <> redirect
   rename.io.roqCommits <> roq.io.commits
   rename.io.in <> decBuf.io.out
-  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr
+  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.memIntRf.map(_.addr)
   rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
-  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
+  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.memFpRf.map(_.addr)
   rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
   rename.io.replayPregReq <> dispatch.io.replayPregReq
   dispatch.io.redirect <> redirect
@@ -177,8 +177,8 @@ class Backend extends XSModule
   dispatch.io.lsroqIdxs <> io.mem.lsroqIdxs
   dispatch.io.commits <> roq.io.commits
 
-  intRf.io.readPorts <> dispatch.io.readIntRf
-  fpRf.io.readPorts <> dispatch.io.readFpRf
+  intRf.io.readPorts <> dispatch.io.readIntRf ++ dispatch.io.memIntRf
+  fpRf.io.readPorts <> dispatch.io.readFpRf ++ dispatch.io.memFpRf
 
   io.mem.redirect <> redirect
 

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -43,8 +43,8 @@ class Dispatch extends XSModule {
     val intPregRdy = Vec(NRIntReadPorts, Input(Bool()))
     val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
     // load + store reg status (busy/ready)
-    val intMemRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
-    val fpMemRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
+    val memIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort))
+    val memFpRf = Vec(exuParameters.StuCnt, Flipped(new RfReadPort))
     val intMemRegRdy = Vec(NRMemReadPorts, Input(Bool()))
     val fpMemRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
     // replay: set preg status to not ready
@@ -140,8 +140,8 @@ class Dispatch extends XSModule {
   // Load/store dispatch queue to load/store issue queues
   val lsDispatch = Module(new Dispatch2Ls)
   lsDispatch.io.fromDq <> lsDq.io.deq
-  lsDispatch.io.intRegAddr <> io.intMemRegAddr
-  lsDispatch.io.fpRegAddr <> io.fpMemRegAddr
+  lsDispatch.io.readIntRf <> io.memIntRf
+  lsDispatch.io.readFpRf <> io.memFpRf
   lsDispatch.io.intRegRdy <> io.intMemRegRdy
   lsDispatch.io.fpRegRdy <> io.fpMemRegRdy
   lsDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -10,12 +10,15 @@ import xiangshan.backend.exu._
 class Dispatch2Ls extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)))
-    val intRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
-    val fpRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
+    val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
+    val readFpRf = Vec(NRIntReadPorts, Flipped(new RfReadPort))
+    // val intRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    // val fpRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
     val intRegRdy = Vec(NRMemReadPorts, Input(Bool()))
     val fpRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
     val numExist = Input(Vec(exuParameters.LsExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp))
+    val enqIQData = Vec(exuParameters.LsExuCnt, Output(new ExuInput))
   })
 
   /**
@@ -70,12 +73,12 @@ class Dispatch2Ls extends XSModule {
   val readPort = Seq(0, 1, 2, 4)
   for (i <- 0 until exuParameters.LsExuCnt) {
     if (i < exuParameters.LduCnt) {
-      io.intRegAddr(readPort(i)) := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntRf(readPort(i)).addr := io.fromDq(indexVec(i)).bits.psrc1
     }
     else {
-      io.fpRegAddr(i - exuParameters.LduCnt) := io.fromDq(indexVec(i)).bits.psrc2
-      io.intRegAddr(readPort(i)  ) := io.fromDq(indexVec(i)).bits.psrc1
-      io.intRegAddr(readPort(i)+1) := io.fromDq(indexVec(i)).bits.psrc2
+      io.readFpRf(i - exuParameters.LduCnt).addr := io.fromDq(indexVec(i)).bits.psrc2
+      io.readIntRf(readPort(i)  ).addr := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntRf(readPort(i)+1).addr := io.fromDq(indexVec(i)).bits.psrc2
     }
   }
 
@@ -111,4 +114,31 @@ class Dispatch2Ls extends XSModule {
     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Ls dispatch queue with index $i\n")
   }
+
+  /**
+    * Part 5: the second stage of dispatch 2 (send data to reservation station)
+    */
+  val uopReg = Reg(Vec(exuParameters.LsExuCnt, new MicroOp))
+  val dataValidRegDebug = Reg(Vec(exuParameters.LsExuCnt, Bool()))
+  for (i <- 0 until exuParameters.IntExuCnt) {
+    uopReg(i) := io.enqIQCtrl(i).bits
+    dataValidRegDebug(i) := io.enqIQCtrl(i).fire()
+
+    io.enqIQData(i) := DontCare
+    // assert(uopReg(i).ctrl.src1Type =/= SrcType.pc)
+    io.enqIQData(i).src1 := io.readIntRf(readPort(i)).data
+    if (i >= exuParameters.LduCnt) {
+      io.enqIQData(i).src2 := Mux(
+        uopReg(i).ctrl.src2Type === SrcType.imm,
+        uopReg(i).ctrl.imm,
+        Mux(uopReg(i).ctrl.src2Type === SrcType.fp,
+          io.readFpRf(i - exuParameters.LduCnt).data,
+          io.readIntRf(readPort(i) + 1).data))
+    }
+
+    XSDebug(dataValidRegDebug(i),
+      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
+        p"(${readPort(i)  }, ${uopReg(i).psrc1}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
+        p"(${readPort(i)+1}, ${uopReg(i).psrc2}, ${Hexadecimal(io.enqIQData(i).src2)})\n")
+  }
 }