Merge pull request #449 from RISCVERS/perf-debug

Perf: Modify predictor counter logic

.github/workflows/emu.yml

@@ -39,7 +39,7 @@ jobs:
           echo "AM_HOME=/home/ci-runner/xsenv/nexus-am" >> $GITHUB_ENV
       - name: Build EMU
         run:
-          make ./build/emu SIM_ARGS=--disable-all NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME -j220
+          make ./build/emu SIM_ARGS=--disable-log NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME B=0 E=0 -j220
       - name: Run cputest
         run: |
           CPU_TEST_DIR=$AM_HOME/tests/cputest
@@ -49,7 +49,7 @@ jobs:
           do
               t=${test%.c}
               echo $t
-              make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run 2>/dev/null | grep "HIT GOOD TRAP"
+              make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0 | grep "HIT GOOD TRAP"
               if [[ $? != 0 ]];
               then
                   echo $t fail
@@ -59,10 +59,10 @@ jobs:
           exit $ret
       - name: Run riscv-tests
         run: |
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run 2> /dev/null
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run B=0 E=0
       - name: Run microbench
         run: |
-          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run 2> /dev/null
+          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run B=0 E=0
       - name: Run coremark
         run: |
-          make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run 2> /dev/null
+          make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0

src/main/scala/utils/LogUtils.scala

@@ -11,6 +11,7 @@ object XSLogLevel extends Enumeration {
   val ALL   = Value(0, "ALL  ")
   val DEBUG = Value("DEBUG")
   val INFO  = Value("INFO ")
+  val PERF  = Value("PERF ")
   val WARN  = Value("WARN ")
   val ERROR = Value("ERROR")
   val OFF   = Value("OFF  ")
@@ -24,7 +25,9 @@ object XSLog {
   {
     val logEnable = WireInit(false.B)
     val logTimestamp = WireInit(0.U(64.W))
-    if(Parameters.get.envParameters.EnableDebug){
+    val enableDebug = Parameters.get.envParameters.EnableDebug && debugLevel != XSLogLevel.PERF
+    val enablePerf = Parameters.get.envParameters.EnablePerfDebug && debugLevel == XSLogLevel.PERF
+    if (enableDebug || enablePerf) {
       ExcitingUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE")
       ExcitingUtils.addSink(logTimestamp, "logTimestamp")
       when (cond && logEnable) {
@@ -98,3 +101,42 @@ object XSInfo extends LogHelper(XSLogLevel.INFO)
 object XSWarn extends LogHelper(XSLogLevel.WARN)
 
 object XSError extends LogHelper(XSLogLevel.ERROR)
+
+object XSPerf {
+  def apply(perfName: String, perfCnt: UInt)(implicit name: String) = {
+    val reset = true
+    val print_per_cycle = false
+    val print_gap_bits = 15
+
+    val counter = RegInit(0.U(64.W))
+    val next_counter = WireInit(0.U(64.W))
+    val logTimestamp = WireInit(0.U(64.W))
+    val enableDebug = Parameters.get.envParameters.EnableDebug
+    val logEnable = WireInit(false.B)
+
+    if (enableDebug) {
+      ExcitingUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE")
+
+      if(!print_per_cycle) {
+        ExcitingUtils.addSink(logTimestamp, "logTimestamp")
+
+        next_counter := counter + perfCnt
+
+        when(logEnable && logTimestamp(print_gap_bits-1, 0) === 0.U) { // TODO: Need print when program exit?
+          if(reset) {
+            next_counter := perfCnt
+            XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $counter\n")
+          }else{
+            XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $next_counter\n")
+          }
+        }
+
+        counter := next_counter
+      }else{
+        when(logEnable) {
+          XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $perfCnt\n")
+        }
+      }
+    }
+  }
+}

src/main/scala/xiangshan/Bundle.scala

@@ -142,6 +142,8 @@ class BpuMeta extends XSBundle with HasBPUParameter {
   val debug_btb_cycle  = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W)
   val debug_tage_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W)
 
+  val predictor = if (BPUDebug) UInt(log2Up(4).W) else UInt(0.W) // Mark which component this prediction comes from {ubtb, btb, tage, loopPredictor}
+
   // def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = {
   //   this.histPtr := histPtr
   //   this.tageMeta := tageMeta
@@ -160,7 +162,7 @@ class Predecode extends XSBundle with HasIFUConst {
   val pd = Vec(PredictWidth, (new PreDecodeInfo))
 }
 
-class CfiUpdateInfo extends XSBundle {
+class CfiUpdateInfo extends XSBundle with HasBPUParameter {
   // from backend
   val pc = UInt(VAddrBits.W)
   val pnpc = UInt(VAddrBits.W)
@@ -241,6 +243,16 @@ class CfCtrl extends XSBundle {
   val brTag = new BrqPtr
 }
 
+class PerfDebugInfo extends XSBundle {
+  // val fetchTime = UInt(64.W)
+  val renameTime = UInt(64.W)
+  val dispatchTime = UInt(64.W)
+  val issueTime = UInt(64.W)
+  val writebackTime = UInt(64.W)
+  // val commitTime = UInt(64.W)
+}
+
+// Separate LSQ
 class LSIdx extends XSBundle {
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
@@ -254,6 +266,7 @@ class MicroOp extends CfCtrl {
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
   val diffTestDebugLrScValid = Bool()
+  val debugInfo = new PerfDebugInfo
 }
 
 class Redirect extends XSBundle {

src/main/scala/xiangshan/XSCore.scala

@@ -277,7 +277,8 @@ abstract class XSBundle extends Bundle
 case class EnviromentParameters
 (
   FPGAPlatform: Boolean = true,
-  EnableDebug: Boolean = false
+  EnableDebug: Boolean = false,
+  EnablePerfDebug: Boolean = false
 )
 
 // object AddressSpace extends HasXSParameter {

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -234,6 +234,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
     mergeData.brUpdate.target := redirectTarget
     mergeData.brUpdate.brTarget := redirectTarget
     mergeData.brUpdate.taken := wb.brUpdate.taken
+    mergeData.brUpdate.bpuMeta.predictor:= wb.brUpdate.bpuMeta.predictor
     mergeData
   }
 
@@ -314,6 +315,20 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   val mbpRRight = predRight && isRType
   val mbpRWrong = predWrong && isRType
 
+  val predictor = io.cfiInfo.bits.bpuMeta.predictor
+
+  val ubtbRight = !io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 0.U
+  val ubtbWrong =  io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 0.U
+
+  val btbRight  = !io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 1.U
+  val btbWrong  =  io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 1.U
+
+  val tageRight = !io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 2.U
+  val tageWrong =  io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 2.U
+
+  val loopRight = !io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 3.U
+  val loopWrong =  io.cfiInfo.bits.isMisPred && !io.cfiInfo.bits.isReplay && predictor === 3.U
+
   if(!env.FPGAPlatform){
     ExcitingUtils.addSource(mbpInstr, "perfCntCondBpInstr", Perf)
     ExcitingUtils.addSource(mbpRight, "perfCntCondBpRight", Perf)
@@ -326,5 +341,28 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
     ExcitingUtils.addSource(mbpIWrong, "perfCntCondBpIWrong", Perf)
     ExcitingUtils.addSource(mbpRRight, "perfCntCondBpRRight", Perf)
     ExcitingUtils.addSource(mbpRWrong, "perfCntCondBpRWrong", Perf)
+
+    ExcitingUtils.addSource(ubtbRight, "perfCntubtbRight", Perf)
+    ExcitingUtils.addSource(ubtbWrong, "perfCntubtbWrong", Perf)
+    ExcitingUtils.addSource(btbRight, "perfCntbtbRight", Perf)
+    ExcitingUtils.addSource(btbWrong, "perfCntbtbWrong", Perf)
+    ExcitingUtils.addSource(tageRight, "perfCnttageRight", Perf)
+    ExcitingUtils.addSource(tageWrong, "perfCnttageWrong", Perf)
+    ExcitingUtils.addSource(loopRight, "perfCntloopRight", Perf)
+    ExcitingUtils.addSource(loopWrong, "perfCntloopWrong", Perf)
   }
+
+  val utilization = Mux(headPtr.flag === tailPtr.flag, tailPtr.value - headPtr.value, BrqSize.U + tailPtr.value - headPtr.value)
+  XSPerf("utilization", utilization)
+  XSPerf("mbpInstr", PopCount(mbpInstr))
+  XSPerf("mbpRight", PopCount(mbpRight))
+  XSPerf("mbpWrong", PopCount(mbpWrong))
+  XSPerf("mbpBRight", PopCount(mbpBRight))
+  XSPerf("mbpBWrong", PopCount(mbpBWrong))
+  XSPerf("mbpJRight", PopCount(mbpJRight))
+  XSPerf("mbpJWrong", PopCount(mbpJWrong))
+  XSPerf("mbpIRight", PopCount(mbpIRight))
+  XSPerf("mbpIWrong", PopCount(mbpIWrong))
+  XSPerf("mbpRRight", PopCount(mbpRRight))
+  XSPerf("mbpRWrong", PopCount(mbpRWrong))
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.ExcitingUtils._
 import xiangshan._
-import utils.{XSDebug, XSError, XSInfo}
+import utils._
 import xiangshan.backend.roq.{RoqPtr, RoqEnqIO}
 import xiangshan.backend.rename.RenameBypassInfo
 import xiangshan.mem.LsqEnqIO
@@ -198,4 +198,7 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     PopCount(io.toFpDq.req.map(_.valid && io.toFpDq.canAccept)) +
     PopCount(io.toLsDq.req.map(_.valid && io.toLsDq.canAccept))
   XSError(enqFireCnt > renameFireCnt, "enqFireCnt should not be greater than renameFireCnt\n")
+
+  XSPerf("utilization", PopCount(io.fromRename.map(_.valid)))
+  XSPerf("waitInstr", PopCount((0 until RenameWidth).map(i => io.fromRename(i).valid && !io.recv(i))))
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -125,4 +125,7 @@ class Dispatch2Fp extends XSModule {
 //        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc2}, ${Hexadecimal(io.enqIQData(i).src2)}), " +
 //        p"(${readPortIndexReg(i)+2.U}, ${uopReg(i).psrc3}, ${Hexadecimal(io.enqIQData(i).src3)})\n")
 //  }
+
+  XSPerf("utilization", PopCount(io.fromDq.map(_.valid)))
+
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -135,4 +135,7 @@ class Dispatch2Int extends XSModule {
 //        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc1}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
 //        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc2}, ${Hexadecimal(io.enqIQData(i).src2)})\n")
 //  }
+
+  XSPerf("utilization", PopCount(io.fromDq.map(_.valid)))
+
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -134,4 +134,8 @@ class Dispatch2Ls extends XSModule {
 //        p"(${readPort(i)  }, ${uopReg(i).psrc1}, ${Hexadecimal(io.enqIQData(i).src1)}), " +
 //        p"(${readPort(i)+1}, ${uopReg(i).psrc2}, ${Hexadecimal(io.enqIQData(i).src2)})\n")
 //  }
+
+  XSPerf("utilization", PopCount(io.fromDq.map(_.valid)))
+  XSPerf("waitInstr", PopCount(io.fromDq.map(r => r.valid && !r.ready)))
+
 }

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -204,4 +204,5 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule with H
   XSDebug(false, true.B, "\n")
 
   XSError(isAfter(headPtr(0), tailPtr(0)), p"assert greaterOrEqualThan(tailPtr: ${tailPtr(0)}, headPtr: ${headPtr(0)}) failed\n")
+  XSPerf("utilization", PopCount(stateEntries.map(_ =/= s_invalid)))
 }

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -791,12 +791,16 @@ class CSR extends FunctionUnit with HasCSRConst
     "PtwCycleCnt" -> (0x1026, "perfCntPtwCycleCnt"  ),
     "PtwL2TlbHit" -> (0x1027, "perfCntPtwL2TlbHit"  ),
     "ICacheReq"   -> (0x1028, "perfCntIcacheReqCnt" ),
-    "ICacheMiss"  -> (0x1029, "perfCntIcacheMissCnt")
-    // "FetchFromICache" -> (0x102a, "CntFetchFromICache"),
-    // "FetchFromLoopBuffer" -> (0x102b, "CntFetchFromLoopBuffer"),
-    // "ExitLoop1" -> (0x102c, "CntExitLoop1"),
-    // "ExitLoop2" -> (0x102d, "CntExitLoop2"),
-    // "ExitLoop3" -> (0x102e, "CntExitLoop3")
+    "ICacheMiss"  -> (0x1029, "perfCntIcacheMissCnt"),
+    
+    "ubtbRight"   -> (0x1030, "perfCntubtbRight"),
+    "ubtbWrong"   -> (0x1031, "perfCntubtbWrong"),
+    "btbRight"    -> (0x1032, "perfCntbtbRight"),
+    "btbWrong"    -> (0x1033, "perfCntbtbWrong"),
+    "tageRight"   -> (0x1034, "perfCnttageRight"),
+    "tageWrong"   -> (0x1035, "perfCnttageWrong"),
+    "loopRight"   -> (0x1036, "perfCntloopRight"),
+    "loopWrong"   -> (0x1037, "perfCntloopWrong")
     // "L2cacheHit" -> (0x1023, "perfCntCondL2cacheHit")
   ) ++ (
     (0 until dcacheParameters.nMissEntries).map(i =>

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.rename
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import utils.XSInfo
+import utils._
 
 class RenameBypassInfo extends XSBundle {
   val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))
@@ -77,6 +77,7 @@ class Rename extends XSModule {
     uop.src3State := DontCare
     uop.roqIdx := DontCare
     uop.diffTestDebugLrScValid := DontCare
+    uop.debugInfo := DontCare
     uop.lqIdx := DontCare
     uop.sqIdx := DontCare
   })

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -315,6 +315,8 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
       debug_microOp(wbIdx).diffTestDebugLrScValid := io.exeWbResults(i).bits.uop.diffTestDebugLrScValid
       debug_exuData(wbIdx) := io.exeWbResults(i).bits.data
       debug_exuDebug(wbIdx) := io.exeWbResults(i).bits.debug
+      debug_microOp(wbIdx).debugInfo.issueTime := io.exeWbResults(i).bits.uop.debugInfo.issueTime
+      debug_microOp(wbIdx).debugInfo.writebackTime := io.exeWbResults(i).bits.uop.debugInfo.writebackTime
 
       val debug_Uop = debug_microOp(wbIdx)
       XSInfo(true.B,
@@ -674,6 +676,23 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     if(i % 4 == 3) XSDebug(false, true.B, "\n")
   }
 
+  XSPerf("utilization", PopCount((0 until RoqSize).map(valid(_))))
+  XSPerf("commitInstr", Mux(io.commits.isWalk, 0.U, PopCount(io.commits.valid)))
+  XSPerf("commitInstrLoad", Mux(io.commits.isWalk, 0.U, PopCount(io.commits.valid.zip(io.commits.info.map(_.commitType)).map{ case (v, t) => v && t === CommitType.LOAD})))
+  XSPerf("commitInstrStore", Mux(io.commits.isWalk, 0.U, PopCount(io.commits.valid.zip(io.commits.info.map(_.commitType)).map{ case (v, t) => v && t === CommitType.STORE})))
+  XSPerf("writeback", PopCount((0 until RoqSize).map(i => valid(i) && writebacked(i))))
+  // XSPerf("enqInstr", PopCount(io.dp1Req.map(_.fire())))
+  // XSPerf("d2rVnR", PopCount(io.dp1Req.map(p => p.valid && !p.ready)))
+  XSPerf("walkInstr", Mux(io.commits.isWalk, PopCount(io.commits.valid), 0.U))
+  XSPerf("walkCycle", state === s_walk || state === s_extrawalk)
+  val deqNotWritebacked = valid(deqPtr.value) && !writebacked(deqPtr.value)
+  val deqUopCommitType = io.commits.info(0).commitType
+  XSPerf("waitNormalCycle", deqNotWritebacked && deqUopCommitType === CommitType.NORMAL)
+  XSPerf("waitBranchCycle", deqNotWritebacked && deqUopCommitType === CommitType.BRANCH)
+  XSPerf("waitLoadCycle", deqNotWritebacked && deqUopCommitType === CommitType.LOAD)
+  XSPerf("waitStoreCycle", deqNotWritebacked && deqUopCommitType === CommitType.STORE)
+  XSPerf("roqHeadPC", io.commits.info(0).pc)
+
   val instrCnt = RegInit(0.U(64.W))
   val retireCounter = Mux(state === s_idle, commitCnt, 0.U)
   instrCnt := instrCnt + retireCounter
@@ -751,7 +770,6 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     ExcitingUtils.addSource(RegNext(trapPC), "trapPC")
     ExcitingUtils.addSource(RegNext(GTimer()), "trapCycleCnt")
     ExcitingUtils.addSource(RegNext(instrCnt), "trapInstrCnt")
-    ExcitingUtils.addSource(state === s_walk || state === s_extrawalk, "perfCntCondRoqWalk", Perf)
 
     if(EnableBPU){
       ExcitingUtils.addSource(hitTrap, "XSTRAP", ConnectionType.Debug)

src/main/scala/xiangshan/frontend/IFU.scala

@@ -8,6 +8,7 @@ import utils._
 import xiangshan.cache._
 import chisel3.experimental.chiselName
 import freechips.rocketchip.tile.HasLazyRoCC
+import chisel3.ExcitingUtils._
 
 trait HasIFUConst extends HasXSParameter {
   val resetVector = 0x80000000L//TODO: set reset vec
@@ -476,6 +477,35 @@ class IFU extends XSModule with HasIFUConst
   io.fetchPacket.bits := fetchPacketWire
   io.fetchPacket.valid := fetchPacketValid
 
+//  if(IFUDebug) {
+    val predictor_s3 = RegEnable(Mux(if3_redirect, 1.U(log2Up(4).W), 0.U(log2Up(4).W)), if3_fire)
+    val predictor_s4 = Mux(if4_redirect, 2.U, predictor_s3)
+    val predictor = predictor_s4
+
+    fetchPacketWire.bpuMeta.map(_.predictor := predictor)
+ // }
+
+  // val predRight = cfiUpdate.valid && !cfiUpdate.bits.isMisPred && !cfiUpdate.bits.isReplay
+  // val predWrong = cfiUpdate.valid && cfiUpdate.bits.isMisPred && !cfiUpdate.bits.isReplay
+
+  // val ubtbRight = predRight && cfiUpdate.bits.bpuMeta.predictor === 0.U
+  // val ubtbWrong = predWrong && cfiUpdate.bits.bpuMeta.predictor === 0.U
+  // val btbRight  = predRight && cfiUpdate.bits.bpuMeta.predictor === 1.U
+  // val btbWrong  = predWrong && cfiUpdate.bits.bpuMeta.predictor === 1.U
+  // val tageRight = predRight && cfiUpdate.bits.bpuMeta.predictor === 2.U
+  // val tageWrong = predWrong && cfiUpdate.bits.bpuMeta.predictor === 2.U
+  // val loopRight = predRight && cfiUpdate.bits.bpuMeta.predictor === 3.U
+  // val loopWrong = predWrong && cfiUpdate.bits.bpuMeta.predictor === 3.U
+
+  // ExcitingUtils.addSource(ubtbRight, "perfCntubtbRight", Perf)
+  // ExcitingUtils.addSource(ubtbWrong, "perfCntubtbWrong", Perf)
+  // ExcitingUtils.addSource(btbRight, "perfCntbtbRight", Perf)
+  // ExcitingUtils.addSource(btbWrong, "perfCntbtbWrong", Perf)
+  // ExcitingUtils.addSource(tageRight, "perfCnttageRight", Perf)
+  // ExcitingUtils.addSource(tageWrong, "perfCnttageWrong", Perf)
+  // ExcitingUtils.addSource(loopRight, "perfCntloopRight", Perf)
+  // ExcitingUtils.addSource(loopWrong, "perfCntloopWrong", Perf)
+
   // debug info
   if (IFUDebug) {
     XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n")
@@ -487,6 +517,7 @@ class IFU extends XSModule with HasIFUConst
     XSDebug("[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x snpc=%x\n", if2_valid, if2_ready, if2_fire, if2_redirect, if2_flush, if2_pc, if2_snpc)
     XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, crossPageIPF, if3_bp.hasNotTakenBrs)
     XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x crossPageIPF=%d sawNTBrs=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_crossPageIPF, if4_bp.hasNotTakenBrs)
+    XSDebug("[predictor] predictor_s3=%d, predictor_s4=%d, predictor=%d\n", predictor_s3, predictor_s4, predictor)
     XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", icache.io.req.valid, icache.io.req.ready, icache.io.req.bits.addr)
     XSDebug("[IF1][ghr] hist=%b\n", if1_gh.asUInt)
     XSDebug("[IF1][ghr] extHist=%b\n\n", if1_gh.asUInt)
@@ -528,4 +559,4 @@ class IFU extends XSModule with HasIFUConst
       )
     }
   }
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -206,4 +206,6 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
   //       ibuf(i*8+7).inst
   //   )
   // }
+
+  XSPerf("utilization", validEntries)
 }

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -197,6 +197,7 @@ class LoadQueue extends XSModule
         val dcacheMissed = io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio
         miss(loadWbIndex) := dcacheMissed
         pending(loadWbIndex) := io.loadIn(i).bits.mmio
+        uop(loadWbIndex).debugInfo.issueTime := io.loadIn(i).bits.uop.debugInfo.issueTime
       }
     }
 

src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala

@@ -483,4 +483,6 @@ class Sbuffer extends XSModule with HasSBufferConst {
   cache.zipWithIndex.foreach { case (line, i) => {
     XSDebug(line.valid, "[#%d line] Tag: %x, data: %x, mask: %x\n", i.U, line.tag, line.data.asUInt(), line.mask.asUInt())
   }}
+
+  XSPerf("waitResp", waitingCacheLine.valid)
 }

src/test/scala/xiangshan/testutils/AddSinks.scala

@@ -31,7 +31,15 @@ object AddSinks {
       "perfCntCondMbpIWrong",
       "perfCntCondMbpRRight",
       "perfCntCondMbpRWrong",
-      "perfCntLoopExit"//,
+      "perfCntubtbRight",
+      "perfCntubtbWrong",
+      "perfCntbtbRight",
+      "perfCntbtbWrong",
+      "perfCnttageRight",
+      "perfCnttageWrong",
+      "perfCntloopRight",
+      "perfCntloopWrong",
+      "perfCntLoopExit",
       // "CntFetchFromICache",
       // "CntFetchFromLoopBuffer",
       // "CntExitLoop1",