busytable: moved out of rename

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
-import xiangshan.backend.rename.Rename
+import xiangshan.backend.rename.{Rename, BusyTable}
 import xiangshan.backend.brq.Brq
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
@@ -59,9 +59,8 @@ class CtrlBlock extends XSModule {
   val decBuf = Module(new DecodeBuffer)
   val rename = Module(new Rename)
   val dispatch = Module(new Dispatch)
-  // TODO: move busyTable to dispatch1
-  // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts))
-  // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts))
+  val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts))
+  val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts))
 
   val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1
 
@@ -99,14 +98,6 @@ class CtrlBlock extends XSModule {
 
   rename.io.redirect <> redirect
   rename.io.roqCommits <> roq.io.commits
-  // they should be moved to busytables
-  rename.io.wbIntResults <> io.fromIntBlock.wbRegs
-  rename.io.wbFpResults <> io.fromFpBlock.wbRegs
-  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
-  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
-  rename.io.intPregRdy <> dispatch.io.intPregRdy
-  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
-  rename.io.replayPregReq <> dispatch.io.replayPregReq
   rename.io.out <> dispatch.io.fromRename
 
   dispatch.io.redirect <> redirect
@@ -121,11 +112,39 @@ class CtrlBlock extends XSModule {
   )
   dispatch.io.readIntRf <> io.toIntBlock.readRf
   dispatch.io.readFpRf <> io.toFpBlock.readRf
+  dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) =>
+    intBusyTable.io.allocPregs(i).valid := preg.isInt
+    fpBusyTable.io.allocPregs(i).valid := preg.isInt
+    intBusyTable.io.allocPregs(i).bits := preg.preg
+    fpBusyTable.io.allocPregs(i).bits := preg.preg
+  }
   dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist
   dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl
   dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData
 
 
+  val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe)
+  fpBusyTable.io.flush := flush
+  intBusyTable.io.flush := flush
+  for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){
+    setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U)
+    setPhyRegRdy.bits := wb.bits.uop.pdest
+  }
+  for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){
+    setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen
+    setPhyRegRdy.bits := wb.bits.uop.pdest
+  }
+  intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr)
+  intBusyTable.io.pregRdy <> dispatch.io.intPregRdy
+  fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr)
+  fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy
+  for(i <- 0 until ReplayWidth){
+    intBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isInt
+    fpBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isFp
+    intBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg
+    fpBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg
+  }
+
   roq.io.memRedirect <> io.fromLsBlock.replay
   roq.io.brqRedirect <> brq.io.redirect
   roq.io.dp1Req <> dispatch.io.toRoq

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -45,6 +45,7 @@ class Dispatch extends XSModule {
     val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
     // replay: set preg status to not ready
     val replayPregReq = Output(Vec(ReplayWidth, new ReplayPregReq))
+    val allocPregs = Vec(RenameWidth, Output(new ReplayPregReq))
     // to reservation stations
     val numExist = Input(Vec(exuParameters.ExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))
@@ -71,6 +72,7 @@ class Dispatch extends XSModule {
   dispatch1.io.toIntDq <> intDq.io.enq
   dispatch1.io.toFpDq <> fpDq.io.enq
   dispatch1.io.toLsDq <> lsDq.io.enq
+  dispatch1.io.allocPregs <> io.allocPregs
 
   // dispatch queue: queue uops and dispatch them to different reservation stations or issue queues
   // it may cancel the uops

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -22,6 +22,7 @@ class Dispatch1 extends XSModule {
     val toLsq = Vec(RenameWidth, DecoupledIO(new MicroOp))
     // get LsIdx
     val lsIdx = Input(Vec(RenameWidth, new LSIdx))
+    val allocPregs = Vec(RenameWidth, Output(new ReplayPregReq))
     // to dispatch queue
     val toIntDq = Vec(dpParams.DqEnqWidth, DecoupledIO(new MicroOp))
     val toFpDq = Vec(dpParams.DqEnqWidth, DecoupledIO(new MicroOp))
@@ -147,6 +148,10 @@ class Dispatch1 extends XSModule {
     */
   val readyVector = (0 until RenameWidth).map(i => !io.fromRename(i).valid || io.recv(i))
   for (i <- 0 until RenameWidth) {
+    io.allocPregs(i).isInt := io.fromRename(i).valid && io.fromRename(i).bits.ctrl.rfWen && (io.fromRename(i).bits.ctrl.ldest =/= 0.U)
+    io.allocPregs(i).isFp  := io.fromRename(i).valid && io.fromRename(i).bits.ctrl.fpWen
+    io.allocPregs(i).preg  := io.fromRename(i).bits.pdest
+
     val enqFire = (io.toIntDq(intIndex.io.reverseMapping(i).bits).fire() && intIndex.io.reverseMapping(i).valid) ||
       (io.toFpDq(fpIndex.io.reverseMapping(i).bits).fire() && fpIndex.io.reverseMapping(i).valid) ||
       (io.toLsDq(lsIndex.io.reverseMapping(i).bits).fire() && lsIndex.io.reverseMapping(i).valid)

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -9,14 +9,6 @@ class Rename extends XSModule {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit)))
-    val wbIntResults = Vec(NRIntWritePorts, Flipped(ValidIO(new ExuOutput)))
-    val wbFpResults = Vec(NRFpWritePorts, Flipped(ValidIO(new ExuOutput)))
-    val intRfReadAddr = Vec(NRIntReadPorts, Input(UInt(PhyRegIdxWidth.W)))
-    val fpRfReadAddr = Vec(NRFpReadPorts, Input(UInt(PhyRegIdxWidth.W)))
-    val intPregRdy = Vec(NRIntReadPorts, Output(Bool()))
-    val fpPregRdy = Vec(NRFpReadPorts, Output(Bool()))
-    // set preg to busy when replay
-    val replayPregReq = Vec(ReplayWidth, Input(new ReplayPregReq))
     // from decode buffer
     val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl)))
     // to dispatch1
@@ -43,8 +35,6 @@ class Rename extends XSModule {
   val fpFreeList, intFreeList = Module(new FreeList).io
   val fpRat = Module(new RenameTable(float = true)).io
   val intRat = Module(new RenameTable(float = false)).io
-  val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)).io
-  val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)).io
 
   fpFreeList.redirect := io.redirect
   intFreeList.redirect := io.redirect
@@ -52,8 +42,6 @@ class Rename extends XSModule {
   val flush = io.redirect.valid && (io.redirect.bits.isException || io.redirect.bits.isFlushPipe) // TODO: need check by JiaWei
   fpRat.flush := flush
   intRat.flush := flush
-  fpBusyTable.flush := flush
-  intBusyTable.flush := flush
 
   def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = {
     {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)}
@@ -125,7 +113,6 @@ class Rename extends XSModule {
     def writeRat(fp: Boolean) = {
       val rat = if(fp) fpRat else intRat
       val freeList = if(fp) fpFreeList else intFreeList
-      val busyTable = if(fp) fpBusyTable else intBusyTable
       // speculative inst write
       val specWen = freeList.allocReqs(i) && freeList.canAlloc(i)
       // walk back write
@@ -153,9 +140,6 @@ class Rename extends XSModule {
       freeList.deallocReqs(i) := rat.archWritePorts(i).wen
       freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest
 
-      // set phy reg status to busy
-      busyTable.allocPregs(i).valid := specWen
-      busyTable.allocPregs(i).bits := freeList.pdests(i)
     }
 
     writeRat(fp = false)
@@ -190,26 +174,5 @@ class Rename extends XSModule {
   }
 
 
-  def updateBusyTable(fp: Boolean) = {
-    val wbResults = if(fp) io.wbFpResults else io.wbIntResults
-    val busyTable = if(fp) fpBusyTable else intBusyTable
-    for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs)){
-      setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop)
-      setPhyRegRdy.bits := wb.bits.uop.pdest
-    }
-  }
 
-  updateBusyTable(false)
-  updateBusyTable(true)
-
-  intBusyTable.rfReadAddr <> io.intRfReadAddr
-  intBusyTable.pregRdy <> io.intPregRdy
-  for(i <- io.replayPregReq.indices){
-    intBusyTable.replayPregs(i).valid := io.replayPregReq(i).isInt
-    fpBusyTable.replayPregs(i).valid := io.replayPregReq(i).isFp
-    intBusyTable.replayPregs(i).bits := io.replayPregReq(i).preg
-    fpBusyTable.replayPregs(i).bits := io.replayPregReq(i).preg
-  }
-  fpBusyTable.rfReadAddr <> io.fpRfReadAddr
-  fpBusyTable.pregRdy <> io.fpPregRdy
 }