fix poke when vaild but not firing

src/test/scala/cache/TLCTest/TLCAgent.scala

 package cache.TLCTest
 
 import scala.collection.mutable
-import scala.collection.mutable.{ArrayBuffer, ListBuffer, Map, Queue}
-import chipsalliance.rocketchip.config.{Field, Parameters}
+import scala.collection.mutable.{ArrayBuffer, ListBuffer}
+import chipsalliance.rocketchip.config.Parameters
 
 class AddrState extends TLCOp {
   val callerTrans: ListBuffer[TLCCallerTrans] = ListBuffer()
   val calleeTrans: ListBuffer[TLCCalleeTrans] = ListBuffer()
   var masterPerm: BigInt = nothing
-  var myPerm: BigInt = trunk
+  var myPerm: BigInt = nothing
   var data: BigInt = 0
   var dirty: Boolean = false
 
@@ -130,7 +130,7 @@ trait BigIntExtract {
 }
 
 class TLCAgent(ID: Int, addrStateMap: mutable.Map[BigInt, AddrState], serialList: ArrayBuffer[(Int, TLCTrans)])
-              (implicit p:Parameters)
+              (implicit p: Parameters)
   extends TLCOp with BigIntExtract with PermissionTransition {
   val l2params = p(TLCCacheTestKey)
   val beatNum = l2params.blockBytes / l2params.beatBytes
@@ -236,16 +236,16 @@ class TLCSlaveAgent(ID: Int, val maxSink: Int, addrStateMap: mutable.Map[BigInt,
         state.masterPerm = shrinkTarget(r.c.get.param)
         if (r.c.get.opcode == ReleaseData) {
           state.data = r.c.get.data
-          if (state.masterPerm == nothing){
-            insertWrite(addr)//modify data when master is invalid
+          if (state.masterPerm == nothing) {
+            insertWrite(addr) //modify data when master is invalid
           }
           else {
             insertRead(addr)
           }
         }
         else {
-          if (state.masterPerm == nothing){
-            insertWrite(addr)//modify data when master is invalid
+          if (state.masterPerm == nothing) {
+            insertWrite(addr) //modify data when master is invalid
           }
         }
         //serialization point
@@ -335,8 +335,8 @@ class TLCSlaveAgent(ID: Int, val maxSink: Int, addrStateMap: mutable.Map[BigInt,
         assert(state.masterPerm == shrinkFrom(c.param))
         state.masterPerm = shrinkTarget(c.param)
         state.slaveUpdatePendingProbeAck()
-        if (state.masterPerm == nothing){
-          insertWrite(addr)//modify data when master is invalid
+        if (state.masterPerm == nothing) {
+          insertWrite(addr) //modify data when master is invalid
         }
         else {
           insertRead(addr)
@@ -359,8 +359,8 @@ class TLCSlaveAgent(ID: Int, val maxSink: Int, addrStateMap: mutable.Map[BigInt,
         state.masterPerm = shrinkTarget(c.param)
         state.data = c.data
         state.slaveUpdatePendingProbeAck()
-        if (state.masterPerm == nothing){
-          insertWrite(addr)//modify data when master is invalid
+        if (state.masterPerm == nothing) {
+          insertWrite(addr) //modify data when master is invalid
         }
         else {
           insertRead(addr)
@@ -463,6 +463,11 @@ class TLCSlaveAgent(ID: Int, val maxSink: Int, addrStateMap: mutable.Map[BigInt,
     }
   }
 
+  def addProbe(addr:BigInt,targetPerm:BigInt): Unit = {
+    val pro = ProbeCallerTrans()
+    pro.prepareProbe(addr,targetPerm)
+    innerProbe.append(pro)
+  }
 }
 
 class TLCMasterAgent(ID: Int, val maxSource: Int, addrStateMap: mutable.Map[BigInt, AddrState], serialList: ArrayBuffer[(Int, TLCTrans)])
@@ -561,7 +566,7 @@ class TLCMasterAgent(ID: Int, val maxSource: Int, addrStateMap: mutable.Map[BigI
         if (!d.denied) {
           state.myPerm = d.param
           if (state.myPerm == trunk) {
-            insertWrite(addr)//modify data when trunk
+            insertWrite(addr) //modify data when trunk
           }
           else {
             insertRead(addr)
@@ -590,7 +595,7 @@ class TLCMasterAgent(ID: Int, val maxSource: Int, addrStateMap: mutable.Map[BigI
           state.myPerm = d.param
           state.data = d.data
           if (state.myPerm == trunk) {
-            insertWrite(addr)//modify data when trunk
+            insertWrite(addr) //modify data when trunk
           }
           else {
             insertRead(addr)
@@ -727,15 +732,18 @@ class TLCMasterAgent(ID: Int, val maxSource: Int, addrStateMap: mutable.Map[BigI
   def issueA(): Unit = {
     val abandonList = ListBuffer[AcquireCallerTrans]()
     if (sourceAMap.size < maxSource) { //fast check available ID
+      println(sourceAMap)
       val sourceQ = mutable.Queue() ++ List.tabulate(maxSource)(a => BigInt(a)).filterNot(k => sourceAMap.contains(k))
       outerAcquire.foreach { acq =>
         if (!acq.acquireIssued.getOrElse(true)) { //haven't issue acquire
           val addr = acq.a.get.address
           val state = getState(addr)
+          println(s"check issue acquire addr: $addr")
           if (acq.checkNeedGrow(state.myPerm)) { //really need grow
             if (sourceQ.nonEmpty && !banIssueAcquire(addr)) { //has empty sourceid and ok to issue
               //TODO:decide to make full write here, use acqblock for now
               val allocId = sourceQ.dequeue()
+              println(s"issue acquire addr: $addr, souceID = $allocId")
               aQueue.enqMessage(acq.issueAcquireBlock(allocId, state.myPerm))
               //serialization point
               appendSerial(acq)
@@ -770,5 +778,17 @@ class TLCMasterAgent(ID: Int, val maxSource: Int, addrStateMap: mutable.Map[BigI
     aQueue.fireHead()
   }
 
+  def addAcquire(addr: BigInt, targetPerm: BigInt): Unit = {
+    val acq = AcquireCallerTrans()
+    acq.prepareAcquire(addr, targetPerm)
+    outerAcquire.append(acq)
+  }
+
+  def addRelease(addr: BigInt, targetPerm: BigInt): Unit = {
+    val rel = ReleaseCallerTrans()
+    rel.prepareRelease(addr, targetPerm)
+    outerRelease.append(rel)
+  }
+
 
 }
\ No newline at end of file

src/test/scala/cache/TLCTest/TLCTest.scala

@@ -162,8 +162,8 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
               val tmpE = masterAgent.peekE()
               if (tmpE.isDefined) {
                 EChannel_valid = true
+                mio.EChannel.bits.sink.poke(tmpE.get.sink.U)
                 if (EChannel_valid && EChannel_ready) {
-                  mio.EChannel.bits.sink.poke(tmpE.get.sink.U)
                   masterAgent.fireE()
                 }
               }
@@ -188,13 +188,13 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
               val tmpC = masterAgent.peekC()
               if (tmpC.isDefined) {
                 CChannel_valid = true
+                mio.CChannel.bits.opcode.poke(tmpC.get.opcode.U)
+                mio.CChannel.bits.param.poke(tmpC.get.param.U)
+                mio.CChannel.bits.size.poke(tmpC.get.size.U)
+                mio.CChannel.bits.source.poke(tmpC.get.source.U)
+                mio.CChannel.bits.address.poke(tmpC.get.address.U)
+                mio.CChannel.bits.data.poke(tmpC.get.data.U)
                 if (CChannel_valid && CChannel_ready) {
-                  mio.CChannel.bits.opcode.poke(tmpC.get.opcode.U)
-                  mio.CChannel.bits.param.poke(tmpC.get.param.U)
-                  mio.CChannel.bits.size.poke(tmpC.get.size.U)
-                  mio.CChannel.bits.source.poke(tmpC.get.source.U)
-                  mio.CChannel.bits.address.poke(tmpC.get.address.U)
-                  mio.CChannel.bits.data.poke(tmpC.get.data.U)
                   masterAgent.fireC()
                 }
               }
@@ -220,13 +220,15 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
               val tmpA = masterAgent.peekA()
               if (tmpA.isDefined) {
                 AChannel_valid = true
+                println(s"master $i A valid:$AChannel_valid addr:${tmpA.get.address}")
+                mio.AChannel.bits.opcode.poke(tmpA.get.opcode.U)
+                mio.AChannel.bits.param.poke(tmpA.get.param.U)
+                mio.AChannel.bits.size.poke(tmpA.get.size.U)
+                mio.AChannel.bits.source.poke(tmpA.get.source.U)
+                mio.AChannel.bits.address.poke(tmpA.get.address.U)
+                mio.AChannel.bits.mask.poke(tmpA.get.mask.U)
+                mio.AChannel.bits.data.poke(tmpA.get.data.U)
                 if (AChannel_valid && AChannel_ready) {
-                  mio.AChannel.bits.opcode.poke(tmpA.get.opcode.U)
-                  mio.AChannel.bits.param.poke(tmpA.get.param.U)
-                  mio.AChannel.bits.size.poke(tmpA.get.size.U)
-                  mio.AChannel.bits.source.poke(tmpA.get.source.U)
-                  mio.AChannel.bits.address.poke(tmpA.get.address.U)
-                  mio.AChannel.bits.data.poke(tmpA.get.data.U)
                   masterAgent.fireA()
                 }
               }
@@ -260,14 +262,14 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
             val tmpD = slaveAgent.peekD()
             if (tmpD.isDefined) {
               DChannel_valid = true
+              sio.DChannel.bits.opcode.poke(tmpD.get.opcode.U)
+              sio.DChannel.bits.param.poke(tmpD.get.param.U)
+              sio.DChannel.bits.size.poke(tmpD.get.size.U)
+              sio.DChannel.bits.source.poke(tmpD.get.source.U)
+              sio.DChannel.bits.sink.poke(tmpD.get.sink.U)
+              sio.DChannel.bits.denied.poke(tmpD.get.denied.B)
+              sio.DChannel.bits.data.poke(tmpD.get.data.U)
               if (DChannel_valid && DChannel_ready) { //fire
-                sio.DChannel.bits.opcode.poke(tmpD.get.opcode.U)
-                sio.DChannel.bits.param.poke(tmpD.get.param.U)
-                sio.DChannel.bits.size.poke(tmpD.get.size.U)
-                sio.DChannel.bits.source.poke(tmpD.get.source.U)
-                sio.DChannel.bits.sink.poke(tmpD.get.sink.U)
-                sio.DChannel.bits.denied.poke(tmpD.get.denied.B)
-                sio.DChannel.bits.data.poke(tmpD.get.data.U)
                 slaveAgent.fireD()
               }
             }
@@ -292,14 +294,14 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
             val tmpB = slaveAgent.peekB()
             if (tmpB.isDefined) {
               BChannel_valid = true
+              sio.BChannel.bits.opcode.poke(tmpB.get.opcode.U)
+              sio.BChannel.bits.param.poke(tmpB.get.param.U)
+              sio.BChannel.bits.size.poke(tmpB.get.size.U)
+              sio.BChannel.bits.source.poke(tmpB.get.source.U)
+              sio.BChannel.bits.address.poke(tmpB.get.address.U)
+              sio.BChannel.bits.mask.poke(tmpB.get.mask.U)
+              sio.BChannel.bits.data.poke(tmpB.get.data.U)
               if (BChannel_valid && BChannel_ready) {
-                sio.BChannel.bits.opcode.poke(tmpB.get.opcode.U)
-                sio.BChannel.bits.param.poke(tmpB.get.param.U)
-                sio.BChannel.bits.size.poke(tmpB.get.size.U)
-                sio.BChannel.bits.source.poke(tmpB.get.source.U)
-                sio.BChannel.bits.address.poke(tmpB.get.address.U)
-                sio.BChannel.bits.mask.poke(tmpB.get.mask.U)
-                sio.BChannel.bits.data.poke(tmpB.get.data.U)
                 slaveAgent.fireB()
               }
             }
@@ -315,13 +317,14 @@ class TLCCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
               aCh.source = peekBigInt(sio.AChannel.bits.source)
               aCh.address = peekBigInt(sio.AChannel.bits.address)
               aCh.mask = peekBigInt(sio.AChannel.bits.mask)
+              aCh.data = peekBigInt(sio.AChannel.bits.data)
               slaveAgent.fireA(aCh)
             }
             slaveAgent.tickA()
 
             c.clock.step()
           }
-        }.join
+        }.join()
 
         c.clock.setTimeout(1000)
       }

src/test/scala/cache/TLCTest/TLCTransaction.scala

@@ -248,9 +248,9 @@ trait PermissionTransition extends TLCOp {
 }
 
 //Transaction meta data will hide in start message
-abstract class TLCTrans extends TLCOp with PermissionTransition {
+abstract class TLCTrans extends TLCOp with PermissionTransition with BigIntExtract{
   val blockSizeL2 = BigInt(6)
-  val beatFullMask = BigInt(0xffffffff)
+  val beatFullMask = BigInt(prefix ++ Array.fill(4)(0xff.toByte))
 }
 trait TLCCallerTrans extends TLCTrans{
   var transDepend : Option[TLCTrans] = None

src/test/scala/cache/TLCTest/TLSlaveMMIO.scala

@@ -29,9 +29,9 @@ class TLCSlaveMMIO()(implicit p: Parameters) extends LazyModule
     Seq(TLSlaveParameters.v1(
       address            = List(AddressSet(0x0L, 0xffffffffffL)),
       resources          = device.reg,
-      regionType         = RegionType.UNCACHED,
+      regionType         = RegionType.CACHED,
       supportsGet        = TransferSizes(1, blockBytes),
-      supportsPutPartial = TransferSizes(1, blockBytes),
+//      supportsPutPartial = TransferSizes(1, blockBytes),
       supportsPutFull    = TransferSizes(1, blockBytes),
       supportsAcquireT   = TransferSizes(1, blockBytes),
       supportsAcquireB   = TransferSizes(1, blockBytes),