Beu: separate l1plus and icache (#705)

src/main/scala/system/SoC.scala

@@ -45,6 +45,7 @@ class L1CacheErrorInfo extends XSBundle{
 
 class XSL1BusErrors(val nCores: Int) extends  BusErrors {
   val icache = Vec(nCores, new L1CacheErrorInfo)
+  val l1plus = Vec(nCores, new L1CacheErrorInfo)
   val dcache = Vec(nCores, new L1CacheErrorInfo)
 
   override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
@@ -52,6 +53,8 @@ class XSL1BusErrors(val nCores: Int) extends  BusErrors {
       List(
         Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"),
         Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"),
+        Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"),
+        Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"),
         Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"),
         Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error")
       )
@@ -210,6 +213,7 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       xs_core(i).module.io.hartId := i.U
       xs_core(i).module.io.externalInterrupt.mtip := clint.module.io.mtip(i)
       xs_core(i).module.io.externalInterrupt.msip := clint.module.io.msip(i)
+      beu.module.io.errors.l1plus(i) := RegNext(xs_core(i).module.io.l1plus_error)
       beu.module.io.errors.icache(i) := RegNext(xs_core(i).module.io.icache_error)
       beu.module.io.errors.dcache(i) := RegNext(xs_core(i).module.io.dcache_error)
       // xs_core(i).module.io.externalInterrupt.meip := RegNext(RegNext(io.meip(i)))

src/main/scala/top/Top.scala

@@ -52,13 +52,14 @@ class XSCoreWithL2Imp(outer: XSCoreWithL2) extends LazyModuleImp(outer)
   val io = IO(new Bundle {
     val hartId = Input(UInt(64.W))
     val externalInterrupt = new ExternalInterruptIO
-    val icache_error, dcache_error = new L1CacheErrorInfo
+    val l1plus_error, icache_error, dcache_error = new L1CacheErrorInfo
   })
 
   outer.core.module.io.hartId := io.hartId
   outer.core.module.io.externalInterrupt := io.externalInterrupt
   outer.l2prefetcher.module.io.enable := RegNext(outer.core.module.io.l2_pf_enable)
   outer.l2prefetcher.module.io.in <> outer.l2cache.module.io
+  io.l1plus_error <> outer.core.module.io.l1plus_error
   io.icache_error <> outer.core.module.io.icache_error
   io.dcache_error <> outer.core.module.io.dcache_error
 }
@@ -244,6 +245,7 @@ class XSTop()(implicit p: config.Parameters) extends BaseXSSoc()
       core_with_l2(i).module.io.externalInterrupt.mtip := clint.module.io.mtip(i)
       core_with_l2(i).module.io.externalInterrupt.msip := clint.module.io.msip(i)
       core_with_l2(i).module.io.externalInterrupt.meip := plic.module.io.extra.get.meip(i)
+      beu.module.io.errors.l1plus(i) := RegNext(core_with_l2(i).module.io.l1plus_error)
       beu.module.io.errors.icache(i) := RegNext(core_with_l2(i).module.io.icache_error)
       beu.module.io.errors.dcache(i) := RegNext(core_with_l2(i).module.io.dcache_error)
     }

src/main/scala/xiangshan/XSCore.scala

@@ -340,7 +340,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
     val hartId = Input(UInt(64.W))
     val externalInterrupt = new ExternalInterruptIO
     val l2_pf_enable = Output(Bool())
-    val icache_error, dcache_error = Output(new L1CacheErrorInfo)
+    val l1plus_error, icache_error, dcache_error = Output(new L1CacheErrorInfo)
   })
 
   val difftestIO = IO(new DifftestBundle())
@@ -377,16 +377,8 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   val l1pluscache = outer.l1pluscache.module
   val ptw = outer.ptw.module
 
-  //TODO: connect these signals
-  def errorOR(src1: L1CacheErrorInfo, src2: L1CacheErrorInfo) : L1CacheErrorInfo = {
-    val out = Wire(new L1CacheErrorInfo)
-    out.ecc_error.valid := src1.ecc_error.valid || src2.ecc_error.valid
-    out.ecc_error.bits := true.B
-    out.paddr.valid := out.ecc_error.valid
-    out.paddr.bits := Mux(src1.ecc_error.valid, src1.paddr.bits, src2.paddr.bits)
-    out
-  }
-  io.icache_error <> errorOR(src1=frontend.io.error, src2=l1pluscache.io.error)
+  io.l1plus_error <> l1pluscache.io.error
+  io.icache_error <> frontend.io.error
   io.dcache_error <> memBlock.io.error
 
   frontend.io.backend <> ctrlBlock.io.frontend

src/main/scala/xiangshan/cache/L1plusCache.scala

@@ -408,7 +408,7 @@ class L1plusCacheImp(outer: L1plusCache) extends LazyModuleImp(outer) with HasL1
 
   // response
   io.resp           <> resp_arb.io.out
-  io.error          <> pipe.io.error
+  io.error          <> RegNext(pipe.io.error)
   resp_arb.io.in(0) <> pipe.io.resp
   resp_arb.io.in(1) <> missQueue.io.resp
 

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -96,7 +96,7 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   // ifu to backend
   io.backend.fetchInfo <> ifu.io.toFtq
 
-  io.error <> ifu.io.error
+  io.error <> RegNext(ifu.io.error)
 
   // for(out <- ibuffer.io.out){
   //   XSInfo(out.fire(),
@@ -106,4 +106,4 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
 
   val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid))
   XSPerf("FrontendBubble", frontendBubble)
-}
\ No newline at end of file
+}