RS: use rsIdx for feedback other than roqIdx

src/main/scala/xiangshan/Bundle.scala

@@ -384,7 +384,7 @@ class RoqCommitIO extends XSBundle {
 }
 
 class TlbFeedback extends XSBundle {
-  val roqIdx = new RoqPtr
+  val rsIdx = UInt(log2Up(IssQueSize).W)
   val hit = Bool()
 }
 

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -107,7 +107,7 @@ class FloatBlock
     exeUnits(i).io.redirect <> redirect
     exeUnits(i).io.flush <> flush
     exeUnits(i).io.fromFp <> rs.io.deq
-    rs.io.feedback := DontCare
+    // rs.io.memfeedback := DontCare
 
     rs.suggestName(s"rs_${cfg.name}")
 

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -188,7 +188,7 @@ class IntegerBlock
     exeUnits(i).io.redirect <> redirect
     exeUnits(i).io.fromInt <> rs.io.deq
     exeUnits(i).io.flush <> flush
-    rs.io.feedback := DontCare
+    // rs.io.memfeedback := DontCare
 
     rs.suggestName(s"rs_${cfg.name}")
 

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -172,7 +172,7 @@ class MemBlockImp
 
     // exeUnits(i).io.redirect <> redirect
     // exeUnits(i).io.fromInt <> rs.io.deq
-    rs.io.feedback := DontCare
+    rs.io.memfeedback := DontCare
 
     rs.suggestName(s"rsd_${cfg.name}")
 
@@ -215,7 +215,8 @@ class MemBlockImp
   for (i <- 0 until exuParameters.LduCnt) {
     loadUnits(i).io.redirect      <> io.fromCtrlBlock.redirect
     loadUnits(i).io.flush         <> io.fromCtrlBlock.flush
-    loadUnits(i).io.tlbFeedback   <> reservationStations(i).io.feedback
+    loadUnits(i).io.tlbFeedback   <> reservationStations(i).io.memfeedback
+    loadUnits(i).io.rsIdx         := reservationStations(i).io.rsIdx // TODO: beautify it
     loadUnits(i).io.dtlb          <> dtlb.io.requestor(i)
     // get input form dispatch
     loadUnits(i).io.ldin          <> reservationStations(i).io.deq
@@ -239,7 +240,8 @@ class MemBlockImp
 
     stu.io.redirect    <> io.fromCtrlBlock.redirect
     stu.io.flush       <> io.fromCtrlBlock.flush
-    stu.io.tlbFeedback <> rs.io.feedback
+    stu.io.tlbFeedback <> rs.io.memfeedback
+    stu.io.rsIdx       := rs.io.rsIdx
     stu.io.dtlb        <> dtlbReq
     stu.io.stin        <> rs.io.deq
     stu.io.lsq         <> lsq.io.storeIn(i)
@@ -313,6 +315,7 @@ class MemBlockImp
 
   atomicsUnit.io.in.valid := st0_atomics || st1_atomics
   atomicsUnit.io.in.bits  := Mux(st0_atomics, reservationStations(atomic_rs0).io.deq.bits, reservationStations(atomic_rs1).io.deq.bits)
+  atomicsUnit.io.rsIdx    := Mux(st0_atomics, reservationStations(atomic_rs0).io.rsIdx, reservationStations(atomic_rs1).io.rsIdx)
   atomicsUnit.io.redirect <> io.fromCtrlBlock.redirect
   atomicsUnit.io.flush <> io.fromCtrlBlock.flush
 
@@ -336,12 +339,12 @@ class MemBlockImp
   }
 
   when (state === s_atomics_0) {
-    atomicsUnit.io.tlbFeedback <> reservationStations(atomic_rs0).io.feedback
+    atomicsUnit.io.tlbFeedback <> reservationStations(atomic_rs0).io.memfeedback
 
     assert(!storeUnits(0).io.tlbFeedback.valid)
   }
   when (state === s_atomics_1) {
-    atomicsUnit.io.tlbFeedback <> reservationStations(atomic_rs1).io.feedback
+    atomicsUnit.io.tlbFeedback <> reservationStations(atomic_rs1).io.memfeedback
 
     assert(!storeUnits(1).io.tlbFeedback.valid)
   }

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -109,7 +109,8 @@ class ReservationStation
 
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
-    val feedback = Flipped(ValidIO(new RSFeedback))
+    val memfeedback = if (feedback) Flipped(ValidIO(new RSFeedback)) else null
+    val rsIdx = if (feedback) Output(UInt(log2Up(IssQueSize).W)) else null
   })
 
   val select = Module(new ReservationStationSelect(exuCfg, fastPortsCnt, slowPortsCnt, fixedDelay, fastWakeup, feedback))
@@ -119,12 +120,14 @@ class ReservationStation
   select.io.redirect := io.redirect
   select.io.flush := io.flush
   io.numExist := select.io.numExist
-  select.io.feedbackVec := ctrl.io.feedbackVec
   select.io.redirectVec := ctrl.io.redirectVec
   select.io.readyVec := ctrl.io.readyVec
   select.io.enq.valid := io.fromDispatch.valid
   io.fromDispatch.ready := select.io.enq.ready
   select.io.deq.ready := io.deq.ready
+  if (feedback) {
+    select.io.memfeedback := io.memfeedback
+  }
 
   ctrl.io.in.valid := select.io.enq.fire() && !(io.redirect.valid || io.flush) // NOTE: same as select
   ctrl.io.flush := io.flush
@@ -133,7 +136,6 @@ class ReservationStation
   ctrl.io.validVec := select.io.validVec
   ctrl.io.indexVec := select.io.indexVec
   ctrl.io.redirect := io.redirect
-  ctrl.io.feedback := io.feedback
   ctrl.io.sel.valid := select.io.deq.valid
   ctrl.io.sel.bits  := select.io.deq.bits
   io.fastUopOut := ctrl.io.fastUopOut
@@ -161,6 +163,9 @@ class ReservationStation
     data.io.listen.wdata(i + fastPortsCnt) := io.slowPorts(i).bits.data
   }
 
+  if (feedback) {
+    io.rsIdx := RegNext(select.io.deq.bits) // NOTE: just for feeback
+  }
   io.deq.bits := DontCare
   io.deq.bits.uop  := ctrl.io.out.bits
   io.deq.bits.uop.cf.exceptionVec := 0.U.asTypeOf(ExceptionVec())
@@ -191,8 +196,8 @@ class ReservationStationSelect
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
     val numExist = Output(UInt(iqIdxWidth.W))
+    val memfeedback = if (feedback) Flipped(ValidIO(new RSFeedback)) else null
 
-    val feedbackVec = Input(Vec(IssQueSize+1, Bool()))
     val redirectVec = Input(Vec(IssQueSize, Bool()))
     val readyVec = Input(Vec(IssQueSize, Bool()))
     val validVec = Output(Vec(IssQueSize, Bool()))
@@ -298,12 +303,9 @@ class ReservationStationSelect
       when (count === 0.U) { stateQueue(i) := s_valid }
     }
     if (feedback) {
-      val feedbackMatchVec = widthMap(i => io.feedbackVec(i) && (stateQueue(i) === s_wait || stateQueue(i)===s_valid)).asUInt
-      val feedbackHit       = io.feedbackVec(iqSize)
-      // feedback
-      when (feedbackMatchVec(i)) {
-        stateQueue(i) := Mux(!feedbackHit, s_replay, s_idle)
-        countQueue(i) := Mux(feedbackHit, count, (replayDelay-1).U)
+      when (io.memfeedback.valid) {
+        stateQueue(io.memfeedback.bits.rsIdx) := Mux(io.memfeedback.bits.hit, s_idle, s_replay)
+        countQueue(io.memfeedback.bits.rsIdx) := Mux(io.memfeedback.bits.hit, count, (replayDelay-1).U)
       }
     }
 
@@ -376,7 +378,6 @@ class ReservationStationCtrl
     val sel = Flipped(ValidIO(UInt(iqIdxWidth.W)))
     val out = ValidIO(new MicroOp)
 
-    val feedbackVec = Output(Vec(IssQueSize+1, Bool()))
     val redirectVec = Output(Vec(IssQueSize, Bool()))
     val readyVec = Output(Vec(IssQueSize, Bool()))
     val validVec = Input(Vec(IssQueSize, Bool()))
@@ -388,8 +389,6 @@ class ReservationStationCtrl
 
     val listen = Output(Vec(srcNum, Vec(iqSize, Vec(fastPortsCnt + slowPortsCnt, Bool()))))
     val enqSrcReady = Output(Vec(srcNum, Bool()))
-
-    val feedback = Flipped(ValidIO(new RSFeedback))
   })
 
   val selValid = io.sel.valid
@@ -470,14 +469,6 @@ class ReservationStationCtrl
   }
   io.out.bits.roqIdx := roqIdx(selPtrReg)
 
-  io.feedbackVec := DontCare
-  if (feedback) {
-    (0 until iqSize).foreach{ i =>
-      io.feedbackVec(i) := roqIdx(i).asUInt === io.feedback.bits.roqIdx.asUInt && io.feedback.valid
-    }
-    io.feedbackVec(iqSize) := io.feedback.bits.hit
-  }
-
   io.fastUopOut := DontCare
   if (fastWakeup) {
     val asynUop = Reg(Vec(iqSize, new fastSendUop))

src/main/scala/xiangshan/mem/Memend.scala

@@ -41,6 +41,7 @@ class LsPipelineBundle extends XSBundle {
   val miss = Bool()
   val tlbMiss = Bool()
   val mmio = Bool()
+  val rsIdx = UInt(log2Up(IssQueSize).W)
 
   val forwardMask = Vec(8, Bool())
   val forwardData = Vec(8, UInt(8.W))

src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala

@@ -13,6 +13,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
     val out           = Decoupled(new ExuOutput)
     val dcache        = new DCacheWordIO
     val dtlb          = new TlbRequestIO
+    val rsIdx         = Input(UInt(log2Up(IssQueSize).W))
     val flush_sbuffer = new SbufferFlushBundle
     val tlbFeedback   = ValidIO(new TlbFeedback)
     val redirect      = Flipped(ValidIO(new Redirect))
@@ -69,7 +70,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
   // since we will continue polling tlb all by ourself
   io.tlbFeedback.valid       := RegNext(RegNext(io.in.valid))
   io.tlbFeedback.bits.hit    := true.B
-  io.tlbFeedback.bits.roqIdx := in.uop.roqIdx
+  io.tlbFeedback.bits.rsIdx  := RegEnable(io.rsIdx, io.in.valid)
 
   // tlb translation, manipulating signals && deal with exception
   when (state === s_tlb) {
@@ -96,7 +97,7 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
       exceptionVec(loadPageFault)       := io.dtlb.resp.bits.excp.pf.ld
       exceptionVec(storeAccessFault)    := io.dtlb.resp.bits.excp.af.st
       exceptionVec(loadAccessFault)     := io.dtlb.resp.bits.excp.af.ld
-      val exception = !addrAligned || 
+      val exception = !addrAligned ||
         io.dtlb.resp.bits.excp.pf.st ||
         io.dtlb.resp.bits.excp.pf.ld ||
         io.dtlb.resp.bits.excp.af.st ||

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -24,13 +24,14 @@ class LoadUnit_S0 extends XSModule {
     val out = Decoupled(new LsPipelineBundle)
     val dtlbReq = DecoupledIO(new TlbReq)
     val dcacheReq = DecoupledIO(new DCacheWordReq)
+    val rsIdx = Input(UInt(log2Up(IssQueSize).W))
   })
 
   val s0_uop = io.in.bits.uop
   val s0_vaddr_old = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN)
   val imm12 = WireInit(s0_uop.ctrl.imm(11,0))
   val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
-  val s0_vaddr_hi = Mux(imm12(11), 
+  val s0_vaddr_hi = Mux(imm12(11),
     Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)),
     Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12))
   )
@@ -71,6 +72,7 @@ class LoadUnit_S0 extends XSModule {
   io.out.bits.mask := s0_mask
   io.out.bits.uop := s0_uop
   io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned
+  io.out.bits.rsIdx := io.rsIdx
 
   io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready)
 
@@ -129,6 +131,7 @@ class LoadUnit_S1 extends XSModule {
   io.out.bits.tlbMiss := s1_tlb_miss
   io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld
   io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld
+  io.out.bits.rsIdx := io.in.bits.rsIdx
 
   io.in.ready := !io.in.valid || io.out.ready
 
@@ -164,7 +167,7 @@ class LoadUnit_S2 extends XSModule with HasLoadHelper {
   // feedback tlb result to RS
   io.tlbFeedback.valid := io.in.valid
   io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio)
-  io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx
+  io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx
 
   val forwardMask = io.out.bits.forwardMask
   val forwardData = io.out.bits.forwardData
@@ -242,6 +245,7 @@ class LoadUnit extends XSModule with HasLoadHelper {
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
     val tlbFeedback = ValidIO(new TlbFeedback)
+    val rsIdx = Input(UInt(log2Up(IssQueSize).W))
     val dcache = new DCacheLoadIO
     val dtlb = new TlbRequestIO()
     val sbuffer = new LoadForwardQueryIO
@@ -255,6 +259,7 @@ class LoadUnit extends XSModule with HasLoadHelper {
   load_s0.io.in <> io.ldin
   load_s0.io.dtlbReq <> io.dtlb.req
   load_s0.io.dcacheReq <> io.dcache.req
+  load_s0.io.rsIdx := io.rsIdx
 
   PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush))
 

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -12,6 +12,7 @@ import xiangshan.cache._
 class StoreUnit_S0 extends XSModule {
   val io = IO(new Bundle() {
     val in = Flipped(Decoupled(new ExuInput))
+    val rsIdx = Input(UInt(log2Up(IssQueSize).W))
     val out = Decoupled(new LsPipelineBundle)
     val dtlbReq = DecoupledIO(new TlbReq)
   })
@@ -20,7 +21,7 @@ class StoreUnit_S0 extends XSModule {
   val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN)
   val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0))
   val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12)
-  val saddr_hi = Mux(imm12(11), 
+  val saddr_hi = Mux(imm12(11),
     Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)),
     Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12))
   )
@@ -44,6 +45,7 @@ class StoreUnit_S0 extends XSModule {
   } // not not touch fp store raw data
   io.out.bits.uop := io.in.bits.uop
   io.out.bits.miss := DontCare
+  io.out.bits.rsIdx := io.rsIdx
   io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0))
   io.out.valid := io.in.valid
   io.in.ready := io.out.ready
@@ -81,11 +83,11 @@ class StoreUnit_S1 extends XSModule {
   // Send TLB feedback to store issue queue
   io.tlbFeedback.valid := io.in.valid
   io.tlbFeedback.bits.hit := !s1_tlb_miss
-  io.tlbFeedback.bits.roqIdx := io.in.bits.uop.roqIdx
+  io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx
   XSDebug(io.tlbFeedback.valid,
     "S1 Store: tlbHit: %d roqIdx: %d\n",
     io.tlbFeedback.bits.hit,
-    io.tlbFeedback.bits.roqIdx.asUInt
+    io.tlbFeedback.bits.rsIdx
   )
 
 
@@ -149,6 +151,7 @@ class StoreUnit extends XSModule {
     val flush = Input(Bool())
     val tlbFeedback = ValidIO(new TlbFeedback)
     val dtlb = new TlbRequestIO()
+    val rsIdx = Input(UInt(log2Up(IssQueSize).W))
     val lsq = ValidIO(new LsPipelineBundle)
     val stout = DecoupledIO(new ExuOutput) // writeback store
   })
@@ -160,6 +163,7 @@ class StoreUnit extends XSModule {
 
   store_s0.io.in <> io.stin
   store_s0.io.dtlbReq <> io.dtlb.req
+  store_s0.io.rsIdx := io.rsIdx
 
   PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush))