[WIP] dispatch: do not need exuConfig form its params

src/main/scala/xiangshan/backend/Backend.scala

@@ -63,11 +63,7 @@ class Backend extends XSModule
   val brq = Module(new Brq)
   val decBuf = Module(new DecodeBuffer)
   val rename = Module(new Rename)
-  val dispatch = Module(new Dispatch(
-    jmpExeUnit.config, aluExeUnits(0).config, mduExeUnits(0).config,
-    fmacExeUnits(0).config, fmiscExeUnits(0).config,
-    ldExeUnitCfg, stExeUnitCfg
-  ))
+  val dispatch = Module(new Dispatch)
   val roq = Module(new Roq(wbSize))
   val intRf = Module(new Regfile(
     numReadPorts = NRIntReadPorts,

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -8,11 +8,9 @@ import xiangshan.backend.rename.Rename
 import xiangshan.backend.brq.Brq
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
-import xiangshan.backend.issue.ReservationStationNew
+import xiangshan.backend.exu.Exu.exuConfigs
 import xiangshan.backend.regfile.RfReadPort
 import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO}
-import xiangshan.mem._
-import xiangshan.backend.fu.FunctionUnit._
 
 class CtrlToIntBlockIO extends XSBundle {
   val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp))
@@ -40,16 +38,7 @@ class CtrlToLsBlockIO extends XSBundle {
   val roqDeqPtr = Input(new RoqPtr)
 }
 
-class CtrlBlock
-(
-  jmpCfg: ExuConfig,
-  aluCfg: ExuConfig,
-  mduCfg: ExuConfig,
-  fmacCfg: ExuConfig,
-  fmiscCfg: ExuConfig,
-  ldCfg: ExuConfig,
-  stCfg: ExuConfig
-) extends XSModule {
+class CtrlBlock extends XSModule {
   val io = IO(new Bundle {
     val frontend = Flipped(new FrontendToBackendIO)
     val fromIntBlock = Flipped(new IntBlockToCtrlIO)
@@ -64,18 +53,17 @@ class CtrlBlock
   val brq = Module(new Brq)
   val decBuf = Module(new DecodeBuffer)
   val rename = Module(new Rename)
-  val dispatch = Module(new Dispatch(
-    jmpCfg, aluCfg, mduCfg,
-    fmacCfg, fmiscCfg,
-    ldCfg, stCfg
-  ))
+  val dispatch = Module(new Dispatch)
   // TODO: move busyTable to dispatch1
   // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts))
   // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts))
-  val roq = Module(new Roq)
 
-  val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock)
-  val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock)
+  val fpWbSize = exuConfigs.count(_.writeFpRf)
+  val intWbSize = exuConfigs.count(_.writeIntRf)
+  // wb int exu + wb fp exu + ldu / stu + brq
+  val roqWbSize = intWbSize + fpWbSize + exuParameters.LduCnt + exuParameters.StuCnt + 1
+
+  val roq = Module(new Roq(roqWbSize))
 
   val redirect = Mux(
     roq.io.redirect.valid,

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -6,7 +6,6 @@ import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
 import chisel3.ExcitingUtils._
-import xiangshan.backend.exu.ExuConfig
 import xiangshan.backend.roq.RoqPtr
 
 case class DispatchParameters
@@ -23,16 +22,7 @@ case class DispatchParameters
   LsDqReplayWidth: Int
 )
 
-class Dispatch
-(
-  jmpCfg: ExuConfig,
-  aluCfg: ExuConfig,
-  mduCfg: ExuConfig,
-  fmacCfg: ExuConfig,
-  fmiscCfg: ExuConfig,
-  ldCfg: ExuConfig,
-  stCfg: ExuConfig
-) extends XSModule {
+class Dispatch extends XSModule {
   val io = IO(new Bundle() {
     // flush or replay
     val redirect = Flipped(ValidIO(new Redirect))
@@ -111,7 +101,7 @@ class Dispatch
   }
 
   // Int dispatch queue to Int reservation stations
-  val intDispatch = Module(new Dispatch2Int(jmpCfg, aluCfg, mduCfg))
+  val intDispatch = Module(new Dispatch2Int)
   intDispatch.io.fromDq <> intDq.io.deq
   intDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i)})
   intDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.intPregRdy(i)})
@@ -120,7 +110,7 @@ class Dispatch
   intDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i)})
 
   // Fp dispatch queue to Fp reservation stations
-  val fpDispatch = Module(new Dispatch2Fp(fmacCfg, fmiscCfg))
+  val fpDispatch = Module(new Dispatch2Fp)
   fpDispatch.io.fromDq <> fpDq.io.deq
   fpDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i)})
   fpDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.fpPregRdy(i)})
@@ -129,7 +119,7 @@ class Dispatch
   fpDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i + exuParameters.IntExuCnt)})
   
   // Load/store dispatch queue to load/store issue queues
-  val lsDispatch = Module(new Dispatch2Ls(ldCfg, stCfg))
+  val lsDispatch = Module(new Dispatch2Ls)
   lsDispatch.io.fromDq <> lsDq.io.deq
   lsDispatch.io.readIntRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i + 8)})
   lsDispatch.io.readFpRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i + 12)})

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -5,9 +5,9 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
-import xiangshan.backend.exu._
+import xiangshan.backend.exu.Exu._
 
-class Dispatch2Fp(fmacCfg: ExuConfig, fmiscCfg: ExuConfig) extends XSModule {
+class Dispatch2Fp extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp)))
     val readRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort))
@@ -26,8 +26,8 @@ class Dispatch2Fp(fmacCfg: ExuConfig, fmiscCfg: ExuConfig) extends XSModule {
   val fmacPriority = PriorityGen((0 until exuParameters.FmacCnt).map(i => io.numExist(i)))
   val fmiscPriority = PriorityGen((0 until exuParameters.FmiscCnt).map(i => io.numExist(i+exuParameters.FmacCnt)))
   for (i <- 0 until dpParams.FpDqDeqWidth) {
-    fmacIndexGen.io.validBits(i) := io.fromDq(i).valid && fmacCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    fmiscIndexGen.io.validBits(i) := io.fromDq(i).valid && fmiscCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    fmacIndexGen.io.validBits(i) := io.fromDq(i).valid && fmacExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    fmiscIndexGen.io.validBits(i) := io.fromDq(i).valid && fmiscExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
 
     // XSDebug(io.fromDq(i).valid,
     //   p"fp dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -4,10 +4,11 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import utils._
+import xiangshan.backend.exu.Exu._
 import xiangshan.backend.regfile.RfReadPort
 import xiangshan.backend.exu._
 
-class Dispatch2Int(jmpCfg: ExuConfig, aluCfg: ExuConfig, mduCfg: ExuConfig) extends XSModule {
+class Dispatch2Int extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)))
     val readRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
@@ -27,9 +28,9 @@ class Dispatch2Int(jmpCfg: ExuConfig, aluCfg: ExuConfig, mduCfg: ExuConfig) exte
   val aluPriority = PriorityGen((0 until exuParameters.AluCnt).map(i => io.numExist(i+exuParameters.JmpCnt)))
   val mduPriority = PriorityGen((0 until exuParameters.MduCnt).map(i => io.numExist(i+exuParameters.JmpCnt+exuParameters.AluCnt)))
   for (i <- 0 until dpParams.IntDqDeqWidth) {
-    jmpIndexGen.io.validBits(i) := io.fromDq(i).valid && jmpCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    aluIndexGen.io.validBits(i) := io.fromDq(i).valid && aluCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    mduIndexGen.io.validBits(i) := io.fromDq(i).valid && mduCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    jmpIndexGen.io.validBits(i) := io.fromDq(i).valid && jumpExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    aluIndexGen.io.validBits(i) := io.fromDq(i).valid && aluExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    mduIndexGen.io.validBits(i) := io.fromDq(i).valid && mulDivExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
     // XSDebug(io.fromDq(i).valid,
     //   p"int dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")
   }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -5,9 +5,9 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
-import xiangshan.backend.exu._
+import xiangshan.backend.exu.Exu._
 
-class Dispatch2Ls(ldCfg: ExuConfig, stCfg: ExuConfig) extends XSModule {
+class Dispatch2Ls extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)))
     val readIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort))
@@ -29,8 +29,8 @@ class Dispatch2Ls(ldCfg: ExuConfig, stCfg: ExuConfig) extends XSModule {
   val loadPriority = PriorityGen((0 until exuParameters.LduCnt).map(i => io.numExist(i)))
   val storePriority = PriorityGen((0 until exuParameters.StuCnt).map(i => io.numExist(i+exuParameters.LduCnt)))
   for (i <- 0 until dpParams.LsDqDeqWidth) {
-    loadIndexGen.io.validBits(i) := io.fromDq(i).valid && ldCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    storeIndexGen.io.validBits(i) := io.fromDq(i).valid && stCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    loadIndexGen.io.validBits(i) := io.fromDq(i).valid && ldExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    storeIndexGen.io.validBits(i) := io.fromDq(i).valid && stExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
 
     // XSDebug(io.fromDq(i).valid,
     //   p"ls dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -70,11 +70,11 @@ case class ExuConfig
   }
 }
 
-abstract class Exu[T <: FunctionUnit](val config: ExuConfig) extends XSModule {
+abstract class Exu(val config: ExuConfig) extends XSModule {
 
   val supportedFunctionUnits = config.fuConfigs.map(_.fuGen).map(gen => Module(gen()))
 
-  val fuSel = supportedFunctionUnits.zip(config.fuConfigs.map(_.fuSel)).map{
+  val fuSel = supportedFunctionUnits.zip(config.fuConfigs.map(_.fuSel)).map {
     case (fu, sel) => sel(fu)
   }
 
@@ -161,7 +161,7 @@ abstract class Exu[T <: FunctionUnit](val config: ExuConfig) extends XSModule {
     if (s.size == 1) {
       s.head._1.io.in.ready
     } else {
-      if(needArbiter){
+      if (needArbiter) {
         Cat(s.map(x => x._1.io.in.ready && x._2)).orR()
       } else {
         Cat(s.map(x => x._1.io.in.ready)).andR()
@@ -187,10 +187,10 @@ abstract class Exu[T <: FunctionUnit](val config: ExuConfig) extends XSModule {
     out.redirectValid := false.B
   }
 
-  if(config.writeFpRf){
+  if (config.writeFpRf) {
     assignDontCares(io.toFp.bits)
   }
-  if(config.writeIntRf){
+  if (config.writeIntRf) {
     assignDontCares(io.toInt.bits)
   }
 }
@@ -209,5 +209,11 @@ object Exu {
   val ldExeUnitCfg = ExuConfig("LoadExu", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0)
   val stExeUnitCfg = ExuConfig("StoreExu", Seq(stuCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue)
 
+  val exuConfigs: Seq[ExuConfig] = jumpExeUnitCfg +: (
+      Seq.fill(exuParameters.AluCnt)(aluExeUnitCfg) ++
+      Seq.fill(exuParameters.MduCnt)(mulDivExeUnitCfg) ++
+      Seq.fill(exuParameters.FmacCnt)(fmacExeUnitCfg) ++
+      Seq.fill(exuParameters.FmiscCnt)(fmiscExeUnitCfg)
+    )
 
 }
\ No newline at end of file