Auipc: get pc in jump unit

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -5,6 +5,7 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import chisel3.ExcitingUtils._
+import xiangshan.backend.JumpOpType
 import xiangshan.backend.decode.ImmUnion
 
 
@@ -75,7 +76,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
     val exuOut = new ExuOutput
   }
 
-  val s_idle :: s_wb :: Nil = Enum(2)
+  val s_idle :: s_wb :: s_auipc_wb :: Nil = Enum(3)
 
   class DecodeEnqBrqData extends Bundle {
     val cfiUpdateInfo = new CfiUpdateInfo
@@ -107,7 +108,8 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   /**
     * write back
     */
-  val wbValid = stateQueue(writebackIdx) === s_wb
+  val wbState = stateQueue(writebackIdx)
+  val wbValid = wbState === s_wb
   val wbEntry = Wire(new ExuOutput)
   val wbIsMisPred = wbEntry.redirect.target =/= wbEntry.brUpdate.pnpc
 
@@ -117,7 +119,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
 
   io.out.valid := wbValid
   io.out.bits := wbEntry
-  when (wbValid) {
+  when (wbValid || wbState === s_auipc_wb) {
     stateQueue(writebackIdx) := s_idle
     writebackPtr_next := writebackPtr + 1.U
   }
@@ -164,7 +166,7 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   /**
     * exu write back
     */
-  for (exuWb <- io.exuRedirectWb) {
+  for ((exuWb, i) <- io.exuRedirectWb.zipWithIndex) {
     when (exuWb.valid) {
       val wbIdx = exuWb.bits.redirect.brTag.value
       XSInfo(
@@ -174,8 +176,14 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
         p"target=${Hexadecimal(exuWb.bits.redirect.target)}\n"
       )
       assert(stateQueue(wbIdx) === s_idle)
-
-      stateQueue(wbIdx) := s_wb
+      if(i == 0){ // jump
+        stateQueue(wbIdx) := Mux(JumpOpType.jumpOpisAuipc(exuWb.bits.uop.ctrl.fuOpType),
+          s_auipc_wb,
+          s_wb
+        )
+      } else { // alu
+        stateQueue(wbIdx) := s_wb
+      }
     }
   }
 

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -5,6 +5,7 @@ import chisel3.util._
 import xiangshan._
 import xiangshan.backend.brq.BrqEnqIO
 import utils._
+import xiangshan.backend.decode.Instructions.{AUIPC, MRET, SRET}
 
 class DecodeStage extends XSModule {
   val io = IO(new Bundle() {
@@ -31,12 +32,14 @@ class DecodeStage extends XSModule {
   for (i <- 0 until DecodeWidth) {
     decoders(i).io.enq.ctrl_flow <> io.in(i).bits
 
-    val isMret = io.in(i).bits.instr === BitPat("b001100000010_00000_000_00000_1110011")
-    val isSret = io.in(i).bits.instr === BitPat("b000100000010_00000_000_00000_1110011")
-    val thisBrqValid = !io.in(i).bits.brUpdate.pd.notCFI || isMret || isSret
+    val isMret = io.in(i).bits.instr === MRET
+    val isSret = io.in(i).bits.instr === SRET
+    val isAuiPc = io.in(i).bits.instr === AUIPC
+    val thisBrqValid = !io.in(i).bits.brUpdate.pd.notCFI || isMret || isSret || isAuiPc
     io.enqBrq.needAlloc(i) := thisBrqValid
     io.enqBrq.req(i).valid := io.in(i).valid && thisBrqValid && io.out(i).ready
-    io.enqBrq.req(i).bits  := decoders(i).io.deq.cf_ctrl.cf
+    io.enqBrq.req(i).bits  := io.in(i).bits
+    io.enqBrq.req(i).bits.instr := decoders(i).io.deq.cf_ctrl.cf.instr
 
     io.out(i).valid      := io.in(i).valid && io.enqBrq.req(i).ready
     io.out(i).bits       := decoders(i).io.deq.cf_ctrl

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -135,7 +135,7 @@ object XDecode extends DecodeConstants {
     REMW    -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, N, SelImm.IMM_X),
     REMUW   -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, N, SelImm.IMM_X),
 
-    AUIPC   -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_U),
+    AUIPC   -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.auipc, Y, N, N, N, N, N, N, SelImm.IMM_U),
     JAL     -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, N, SelImm.IMM_UJ),
     JALR    -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, N, SelImm.IMM_I),
     BEQ     -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, N, SelImm.IMM_SB),

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -45,7 +45,10 @@ class Dispatch1 extends XSModule {
     */
   // valid bits for different dispatch queues
   val isInt    = VecInit(io.fromRename.map(req => FuType.isIntExu(req.bits.ctrl.fuType)))
-  val isBranch = VecInit(io.fromRename.map(req => !req.bits.cf.brUpdate.pd.notCFI))
+  val isBranch = VecInit(io.fromRename.map(req =>
+    // cover auipc (a fake branch)
+    !req.bits.cf.brUpdate.pd.notCFI || FuType.isJumpExu(req.bits.ctrl.fuType)
+  ))
   val isFp     = VecInit(io.fromRename.map(req => FuType.isFpExu (req.bits.ctrl.fuType)))
   val isLs     = VecInit(io.fromRename.map(req => FuType.isMemExu(req.bits.ctrl.fuType)))
   val isStore  = VecInit(io.fromRename.map(req => FuType.isStoreExu(req.bits.ctrl.fuType)))

src/main/scala/xiangshan/backend/fu/Jump.scala

@@ -25,9 +25,9 @@ class Jump extends FunctionUnit with HasRedirectOut {
     io.in.bits.uop
   )
 
-  val offset = SignExt(Mux(JumpOpType.jumpOpIsJal(func),
-    ImmUnion.J.toImm32(immMin),
-    ImmUnion.I.toImm32(immMin)
+  val offset = SignExt(Mux(JumpOpType.jumpOpisJalr(func),
+    ImmUnion.I.toImm32(immMin),
+    ImmUnion.J.toImm32(immMin) // Note: imm of auipc also expanded here
   ), XLEN)
 
   val redirectHit = uop.roqIdx.needFlush(io.redirectIn)
@@ -53,7 +53,7 @@ class Jump extends FunctionUnit with HasRedirectOut {
   brUpdate.taken := true.B
 
   // Output
-  val res = snpc
+  val res = Mux(JumpOpType.jumpOpisAuipc(func), target, snpc)
 
   io.in.ready := io.out.ready
   io.out.valid := valid

src/main/scala/xiangshan/backend/package.scala

@@ -17,12 +17,13 @@ package object backend {
 
   // jump
   object JumpOpType {
-    def jal  = "b11_000".U
-    def jalr = "b11_010".U
+    def jal  = "b00".U
+    def jalr = "b01".U
+    def auipc = "b10".U
 //    def call = "b11_011".U
 //    def ret  = "b11_100".U
-    def jumpOpIsJal(op: UInt) = !op(1)
-    def jumpOpisJalr(op: UInt) = op(1)
+    def jumpOpisJalr(op: UInt) = op(0)
+    def jumpOpisAuipc(op: UInt) = op(1)
   }
 
   object FenceOpType {

src/main/scala/xiangshan/package.scala

@@ -48,10 +48,11 @@ package object xiangshan {
 
     def apply() = UInt(log2Up(num).W)
 
-    def isIntExu(fuType: UInt) =  !fuType(3)
+    def isIntExu(fuType: UInt) = !fuType(3)
+    def isJumpExu(fuType: UInt) = fuType === jmp
     def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U
     def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U
-    def isLoadExu(fuType: UInt) = fuType === ldu || fuType===mou
+    def isLoadExu(fuType: UInt) = fuType === ldu || fuType === mou
     def isStoreExu(fuType: UInt) = fuType === stu
 
     val functionNameMap = Map(