[WIP] Memend: fix mem rf port width, add tlbFeedback

src/main/scala/top/XiangShanStage.scala

@@ -5,7 +5,7 @@ import firrtl.AnnotationSeq
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{HasShellOptions, Shell, ShellOption}
 import firrtl.stage.{FirrtlCli, RunFirrtlTransformAnnotation}
-import xstransforms.ShowPrintTransform
+// import xstransforms.ShowPrintTransform
 import xstransforms.PrintModuleName
 
 case class DisablePrintfAnnotation(m: String) extends NoTargetAnnotation
@@ -78,7 +78,7 @@ object XiangShanStage {
     (new XiangShanStage).execute(
       args,
       annotations ++ Seq(
-        RunFirrtlTransformAnnotation(new ShowPrintTransform),
+        // RunFirrtlTransformAnnotation(new ShowPrintTransform),
         RunFirrtlTransformAnnotation(new PrintModuleName)
       )
     )

src/main/scala/xiangshan/backend/Backend.scala

@@ -58,15 +58,6 @@ class Backend extends XSModule
     hasZero = false
   ))
 
-  // decode.io := DontCare
-  // brq.io := DontCare
-  // decBuf.io := DontCare
-  // rename.io := DontCare
-  // dispatch.io := DontCare
-  // roq.io := DontCare
-  // intRf.io := DontCare
-  // fpRf.io := DontCare
-
   // backend redirect, flush pipeline
   val redirect = Mux(
     roq.io.redirect.valid,
@@ -123,6 +114,7 @@ class Backend extends XSModule
       case otherCfg =>
         exeUnits(i).io.in <> rs.io.deq
         exeUnits(i).io.redirect <> redirect
+        rs.io.tlbFeedback := DontCare
     }
 
     rs
@@ -146,6 +138,7 @@ class Backend extends XSModule
   io.mem.roqDeqPtr := roq.io.roqDeqPtr
   io.mem.ldin <> reservedStations.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
   io.mem.stin <> reservedStations.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
+  io.mem.tlbFeedback <> reservedStations.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.tlbFeedback) ++ reservedStations.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.tlbFeedback)
   jmpExeUnit.io.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException
   jmpExeUnit.io.exception.bits := roq.io.exception
 

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -38,10 +38,10 @@ class Dispatch extends XSModule {
     val commits = Input(Vec(CommitWidth, Valid(new RoqCommit)))
     // read regfile
     val readIntRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort))
-    val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort))
+    val readFpRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort))
     // read reg status (busy/ready)
     val intPregRdy = Vec(NRIntReadPorts - NRMemReadPorts, Input(Bool()))
-    val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
+    val fpPregRdy = Vec(NRFpReadPorts - exuParameters.StuCnt, Input(Bool()))
     // load + store reg status (busy/ready)
     val memIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort))
     val memFpRf = Vec(exuParameters.StuCnt, Flipped(new RfReadPort))

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -64,7 +64,7 @@ class ReservationStation
     val numExist = Output(UInt(iqIdxWidth.W))
 
     // tlb hit, inst can deq, only used in ld/st reservation stations
-    val tlbFeedback = Flipped(ValidIO(new TlbFeedback))
+    val tlbFeedback = Flipped(ValidIO(new TlbFeedback)) // TODO
   })
 
   val srcAllNum = 3

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -44,7 +44,7 @@ class Rename extends XSModule {
   val fpRat = Module(new RenameTable(float = true)).io
   val intRat = Module(new RenameTable(float = false)).io
   val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)).io
-  val intBusyTable = Module(new BusyTable(NRIntReadPorts+NRMemReadPorts, NRIntWritePorts)).io
+  val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)).io
 
   fpFreeList.redirect := io.redirect
   intFreeList.redirect := io.redirect

src/main/scala/xiangshan/mem/Memend.scala

@@ -73,7 +73,7 @@ class MemToBackendIO extends XSBundle {
   // replay all instructions form dispatch
   val replayAll = ValidIO(new Redirect)
   // replay mem instructions form Load Queue/Store Queue
-  val tlbFeedback = Vec(exuParameters.LduCnt + exuParameters.LduCnt, ValidIO(new TlbFeedback))
+  val tlbFeedback = Vec(exuParameters.LduCnt + exuParameters.StuCnt, ValidIO(new TlbFeedback))
   val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
   val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
   val lsIdxs = Output(Vec(RenameWidth, new LSIdx))