Clean up project dependencies (#1282)

* Clean up project dependencies

* Update README

* Fix typo

.gitmodules

 [submodule "rocket-chip"]
 	path = rocket-chip
 	url = https://github.com/OpenXiangShan/rocket-chip.git
-[submodule "chiseltest"]
-	path = chiseltest
-	url = https://github.com/ucb-bar/chisel-testers2.git
-[submodule "api-config-chipsalliance"]
-	path = api-config-chipsalliance
-	url = https://github.com/chipsalliance/api-config-chipsalliance.git
-[submodule "berkeley-hardfloat"]
-	path = berkeley-hardfloat
-	url = https://github.com/OpenXiangShan/berkeley-hardfloat.git
 [submodule "difftest"]
 	path = difftest
 	url = https://github.com/OpenXiangShan/difftest.git

Makefile

@@ -98,6 +98,7 @@ clean:
 
 init:
 	git submodule update --init
+	cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
 
 bump:
 	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"

README.md

@@ -41,13 +41,11 @@ Some of the key directories are shown below.
 
 ```
 .
-├── fpga                   # supported FPGA boards and files to build a Vivado project
 ├── read-to-run            # pre-built simulation images
 ├── scripts                # scripts for agile development
 └── src
     ├── test               # test files (including diff-test, module-test, etc.)
     └── main/scala         # design files
-        ├── bus/tilelink   # tilelink utils
         ├── device         # virtual device for simulation
         ├── difftest       # diff-test chisel interface
         ├── system         # SoC wrapper
@@ -100,9 +98,8 @@ In the development of XiangShan, some sub-modules from the open-source community
 
 | Sub-module         | Source                                                       | Detail                                                       |
 | ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
-| L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. |
+| L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. |
 | Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
-| FPU                | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. |
 
 We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).
 

api-config-chipsalliance @ fd8df110

-Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4

berkeley-hardfloat @ 8031f859

-Subproject commit 8031f8594278967d57016ba52a48393662abeb05

build.sc

@@ -17,112 +17,147 @@
 import os.Path
 import mill._
 import scalalib._
+import publish._
 import coursier.maven.MavenRepository
+import $file.`rocket-chip`.common
+import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
+import $file.`rocket-chip`.hardfloat.build
+
+object ivys {
+  val sv = "2.12.13"
+  val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0-RC1"
+  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0-RC1"
+  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.3.2"
+  val scalatest = ivy"org.scalatest::scalatest:3.2.2"
+  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
+}
 
-trait CommonModule extends ScalaModule {
-  override def scalaVersion = "2.12.10"
+trait XSModule extends ScalaModule with PublishModule {
 
-  override def scalacOptions = Seq("-Xsource:2.11")
+  // override this to use chisel from source
+  def chiselOpt: Option[PublishModule] = None
 
-  private val macroParadise = ivy"org.scalamacros:::paradise:2.1.0"
+  override def scalaVersion = ivys.sv
 
-  override def compileIvyDeps = Agg(macroParadise)
+  override def compileIvyDeps = Agg(ivys.macroParadise)
 
-  override def scalacPluginIvyDeps = Agg(macroParadise)
+  override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.chisel3Plugin)
 
-  override def repositoriesTask = T.task {
-    super.repositoriesTask() ++ Seq(
-      MavenRepository("https://oss.sonatype.org/content/repositories/snapshots")
-    )
-  }
+  override def scalacOptions = Seq("-Xsource:2.11")
 
-}
+  override def ivyDeps = if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]
 
-val chisel = Agg(
-  ivy"edu.berkeley.cs::chisel3:3.5.0-RC1"
-)
+  override def moduleDeps = Seq() ++ chiselOpt
 
-object `api-config-chipsalliance` extends CommonModule {
-  override def millSourcePath = super.millSourcePath / "design" / "craft"
-}
+  def publishVersion = "0.0.1"
 
-object hardfloat extends SbtModule with CommonModule {
-  override def millSourcePath = os.pwd / "berkeley-hardfloat"
-  override def ivyDeps = super.ivyDeps() ++ chisel
+  // TODO: fix this
+  def pomSettings = PomSettings(
+    description = "XiangShan",
+    organization = "",
+    url = "https://github.com/OpenXiangShan/XiangShan",
+    licenses = Seq(License.`Apache-2.0`),
+    versionControl = VersionControl.github("OpenXiangShan", "XiangShan"),
+    developers = Seq.empty
+  )
 }
 
-object `rocket-chip` extends SbtModule with CommonModule {
+object rocketchip extends `rocket-chip`.common.CommonRocketChip {
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
-    ivy"org.json4s::json4s-jackson:3.6.1"
-  ) ++ chisel
+  val rcPath = os.pwd / "rocket-chip"
 
-  object macros extends SbtModule with CommonModule
+  override def scalaVersion = ivys.sv
 
-  override def moduleDeps = super.moduleDeps ++ Seq(
-    `api-config-chipsalliance`, macros, hardfloat
-  )
+  override def scalacOptions = Seq("-Xsource:2.11")
 
-}
+  override def millSourcePath = rcPath
 
-object huancun extends SbtModule with CommonModule {
+  object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
+    override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
 
-  override def ivyDeps = super.ivyDeps() ++ chisel
+    override def scalaVersion = T {
+      rocketchip.scalaVersion()
+    }
 
-  override def millSourcePath = super.millSourcePath
+    override def pomSettings = T {
+      rocketchip.pomSettings()
+    }
 
-  override def moduleDeps = super.moduleDeps ++ Seq(
-    `rocket-chip`
-  )
-}
+    override def publishVersion = T {
+      rocketchip.publishVersion()
+    }
+  }
+
+  object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
+    override def millSourcePath = rcPath / "hardfloat"
 
-object chiseltest extends CommonModule with SbtModule {
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    ivy"edu.berkeley.cs::treadle:1.3.0",
-    ivy"org.scalatest::scalatest:3.2.0",
-    ivy"com.lihaoyi::utest:0.7.4"
-  ) ++ chisel
-  object test extends Tests {
-    def ivyDeps = Agg(ivy"org.scalacheck::scalacheck:1.14.3")
-    def testFrameworks = Seq("org.scalatest.tools.Framework")
+    override def scalaVersion = T {
+      rocketchip.scalaVersion()
+    }
+
+    def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
+      common.getVersion("chisel3")
+    ) else Agg.empty[Dep]
   }
+
+  def hardfloatModule = hardfloatRocket
+
+  def configModule = configRocket
+
 }
 
-object difftest extends SbtModule with CommonModule {
-  override def millSourcePath = os.pwd / "difftest"
-  override def ivyDeps = super.ivyDeps() ++ chisel
+object huancun extends XSModule with SbtModule {
+
+  override def millSourcePath = os.pwd / "huancun"
+
+  override def moduleDeps = super.moduleDeps ++ Seq(
+    rocketchip
+  )
 }
 
-object fudian extends CommonModule with SbtModule {
-  override def ivyDeps = super.ivyDeps() ++ chisel
+object difftest extends XSModule with SbtModule {
+  override def millSourcePath = os.pwd / "difftest"
 }
 
-object XiangShan extends CommonModule with SbtModule {
-  override def millSourcePath = millOuterCtx.millSourcePath
+object fudian extends XSModule with SbtModule
+
+// extends this trait to use XiangShan in other projects
+trait CommonXiangShan extends XSModule with SbtModule { m =>
+
+  // module deps
+  def rocketModule: PublishModule
+  def difftestModule: PublishModule
+  def huancunModule: PublishModule
+  def fudianModule: PublishModule
+
+  override def millSourcePath = os.pwd
 
   override def forkArgs = Seq("-Xmx64G", "-Xss256m")
 
-  override def ivyDeps = super.ivyDeps() ++ chisel
+  override def ivyDeps = super.ivyDeps() ++ Seq(ivys.chiseltest)
+
   override def moduleDeps = super.moduleDeps ++ Seq(
-    `rocket-chip`,
-    chiseltest,
-    difftest,
-    huancun,
-    fudian
+    rocketModule,
+    difftestModule,
+    huancunModule,
+    fudianModule
   )
 
-  object test extends Tests {
+  object test extends Tests with TestModule.ScalaTest {
 
-    override def forkArgs = Seq("-Xmx64G", "-Xss256m")
+    override def forkArgs = m.forkArgs
 
     override def ivyDeps = super.ivyDeps() ++ Agg(
-      ivy"org.scalatest::scalatest:3.2.0"
+      ivys.scalatest
     )
 
-    def testFrameworks = Seq(
-      "org.scalatest.tools.Framework"
-    )
   }
 
 }
+
+object XiangShan extends CommonXiangShan {
+  override def rocketModule = rocketchip
+  override def difftestModule = difftest
+  override def huancunModule = huancun
+  override def fudianModule = fudian
+}

chiseltest @ 6a2e1776

-Subproject commit 6a2e1776c91635deb7e1982b2333611ae620e777

rocket-chip @ 95814e3a

-Subproject commit adc3ff94535bf72484a40be353ccfd7915e279d4
+Subproject commit 95814e3a856e9f41d29eb55c4a45694cd5f84531