提交 767926a2 编写于 作者: Fa_wang's avatar Fa_wang

sbuffer: increase evict cycle

上级 ddfb2ee1
......@@ -13,9 +13,9 @@ trait HasSbufferCst extends HasXSParameter {
def s_prepare = 2.U(2.W)
def s_inflight = 3.U(2.W)
val evictCycle = 8192
val evictCycle = 1 << 20
require(isPow2(evictCycle))
val countBits = 1 + log2Up(evictCycle)
val countBits = log2Up(evictCyclei+1)
val SbufferIndexWidth: Int = log2Up(StoreBufferSize)
// paddr = tag + offset
......
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