Backend: fixed the bug when jump unit wakes up store rs (#626)

src/main/scala/xiangshan/XSCore.scala

@@ -346,7 +346,8 @@ class XSCore()(implicit p: config.Parameters) extends LazyModule
     fastWakeUpIn = intExuConfigs.filter(_.hasCertainLatency),
     slowWakeUpIn = intExuConfigs.filter(_.hasUncertainlatency) ++ fpExuConfigs,
     fastWakeUpOut = Seq(),
-    slowWakeUpOut = loadExuConfigs
+    slowWakeUpOut = loadExuConfigs,
+    numIntWakeUpFp = intExuConfigs.count(_.writeFpRf)
   ))
 
   lazy val module = new XSCoreImp(this)
@@ -427,7 +428,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   val intBlockWakeUpFp = intExuConfigs.filter(_.hasUncertainlatency)
     .zip(integerBlock.io.wakeUpOut.slow)
     .filter(_._1.writeFpRf)
-    .map(_._2).map(x => fpOutValid(x, connectReady = true))
+    .map(_._2)
 
   integerBlock.io.wakeUpIn.slow <> fpBlockWakeUpInt ++ memBlockWakeUpInt
   integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
@@ -445,6 +446,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   // Note: 'WireInit' is used to block 'ready's from memBlock,
   // we don't need 'ready's from memBlock
   memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(_.slow.map(x => WireInit(x)))
+  memBlock.io.intWakeUpFp <> floatBlock.io.intWakeUpOut
 
   integerBlock.io.csrio.hartId <> io.hartId
   integerBlock.io.csrio.perf <> DontCare

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -30,6 +30,7 @@ class FloatBlock
     val intWakeUpFp = Vec(intSlowWakeUpIn.size, Flipped(DecoupledIO(new ExuOutput)))
     val memWakeUpFp = Vec(memSlowWakeUpIn.size, Flipped(DecoupledIO(new ExuOutput)))
     val wakeUpOut = Flipped(new WakeUpBundle(fastWakeUpOut.size, slowWakeUpOut.size))
+    val intWakeUpOut = Vec(intSlowWakeUpIn.size, DecoupledIO(new ExuOutput))
 
     // from csr
     val frm = Input(UInt(3.W))
@@ -39,24 +40,28 @@ class FloatBlock
   val flush = io.fromCtrlBlock.flush
 
   val intWakeUpFpReg = Wire(Vec(intSlowWakeUpIn.size, Flipped(DecoupledIO(new ExuOutput))))
-  intWakeUpFpReg.zip(io.intWakeUpFp).foreach{
-    case (inReg, wakeUpIn) =>
-      val in = WireInit(wakeUpIn)
-      wakeUpIn.ready := in.ready
-      in.valid := wakeUpIn.valid && !wakeUpIn.bits.uop.roqIdx.needFlush(redirect, flush)
-      PipelineConnect(in, inReg,
-        inReg.fire() || inReg.bits.uop.roqIdx.needFlush(redirect, flush), false.B
-      )
+  for((w, r) <- io.intWakeUpFp.zip(intWakeUpFpReg)){
+    val in = WireInit(w)
+    w.ready := in.ready
+    in.valid := w.valid && !w.bits.uop.roqIdx.needFlush(redirect, flush)
+    PipelineConnect(in, r, r.fire() || r.bits.uop.roqIdx.needFlush(redirect, flush), false.B)
   }
-  val intRecoded = WireInit(intWakeUpFpReg)
-  for(((rec, reg), cfg) <- intRecoded.zip(intWakeUpFpReg).zip(intSlowWakeUpIn)){
-    rec.bits.data := Mux(reg.bits.uop.ctrl.fpu.typeTagOut === S,
-      recode(reg.bits.data(31, 0), S),
-      recode(reg.bits.data(63, 0), D)
+  // to memBlock's store rs
+  io.intWakeUpOut <> intWakeUpFpReg.map(x => WireInit(x))
+
+  val intRecoded = intWakeUpFpReg.map(x => {
+    val rec = Wire(DecoupledIO(new ExuOutput))
+    rec.valid := x.valid && x.bits.uop.ctrl.fpWen
+    rec.bits := x.bits
+    rec.bits.data := Mux(x.bits.uop.ctrl.fpu.typeTagOut === S,
+      recode(x.bits.data(31, 0), S),
+      recode(x.bits.data(63, 0), D)
     )
     rec.bits.redirectValid := false.B
-    reg.ready := rec.ready || !rec.valid
-  }
+    x.ready := rec.ready || !rec.valid
+    rec
+  })
+
   val memRecoded = WireInit(io.memWakeUpFp)
   for((rec, reg) <- memRecoded.zip(io.memWakeUpFp)){
     rec.bits.data := fpRdataHelper(reg.bits.uop, reg.bits.data)

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -254,8 +254,11 @@ class IntegerBlock
   ))
   intWbArbiter.io.in <> exeUnits.map(e => {
     val w = WireInit(e.io.out)
-    val fpWen = if(e.config.writeFpRf) e.io.out.bits.uop.ctrl.fpWen else false.B
-    w.valid := e.io.out.valid && !fpWen
+    if(e.config.writeFpRf){
+      w.valid := e.io.out.valid && !e.io.out.bits.uop.ctrl.fpWen && io.wakeUpOut.slow(0).ready
+    } else {
+      w.valid := e.io.out.valid
+    }
     w
   }) ++ io.wakeUpIn.slow
 

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -33,7 +33,8 @@ class MemBlock(
   val fastWakeUpIn: Seq[ExuConfig],
   val slowWakeUpIn: Seq[ExuConfig],
   val fastWakeUpOut: Seq[ExuConfig],
-  val slowWakeUpOut: Seq[ExuConfig]
+  val slowWakeUpOut: Seq[ExuConfig],
+  val numIntWakeUpFp: Int
 )(implicit p: Parameters) extends LazyModule {
 
   val dcache = LazyModule(new DCache())
@@ -55,6 +56,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   val slowWakeUpIn = outer.slowWakeUpIn
   val fastWakeUpOut = outer.fastWakeUpOut
   val slowWakeUpOut = outer.slowWakeUpOut
+  val numIntWakeUpFp = outer.numIntWakeUpFp
 
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToLsBlockIO)
@@ -63,6 +65,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     val toCtrlBlock = new LsBlockToCtrlIO
 
     val wakeUpIn = new WakeUpBundle(fastWakeUpIn.size, slowWakeUpIn.size)
+    val intWakeUpFp = Vec(numIntWakeUpFp, Flipped(DecoupledIO(new ExuOutput)))
     val wakeUpOutInt = Flipped(new WakeUpBundle(fastWakeUpOut.size, slowWakeUpOut.size))
     val wakeUpOutFp = Flipped(new WakeUpBundle(fastWakeUpOut.size, slowWakeUpOut.size))
 
@@ -144,14 +147,8 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
       slowWakeUpIn.zip(io.wakeUpIn.slow)
         .filter(x => (x._1.writeIntRf && readIntRf) || (x._1.writeFpRf && readFpRf))
         .map{
-          case (Exu.jumpExeUnitCfg, value) if cfg == Exu.stExeUnitCfg =>
-            val jumpOut = Wire(Flipped(DecoupledIO(new ExuOutput)))
-            jumpOut.bits := RegNext(value.bits)
-            jumpOut.valid := RegNext(
-              value.valid && !value.bits.uop.roqIdx.needFlush(redirect, io.fromCtrlBlock.flush)
-            )
-            jumpOut.ready := true.B
-            (Exu.jumpExeUnitCfg, jumpOut)
+          case (Exu.jumpExeUnitCfg, _) if cfg == Exu.stExeUnitCfg =>
+            (Exu.jumpExeUnitCfg, io.intWakeUpFp.head)
           case (config, value) => (config, value)
         }
     ).map(a => (a._1, decoupledIOToValidIO(a._2)))
@@ -212,6 +209,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   io.wakeUpOutInt.slow <> exeWbReqs
   io.wakeUpOutFp.slow <> wakeUpFp
   io.wakeUpIn.slow.foreach(_.ready := true.B)
+  io.intWakeUpFp.foreach(_.ready := true.B)
 
   val dtlb    = Module(new TLB(Width = DTLBWidth, isDtlb = true))
   val lsq     = Module(new LsqWrappper)