FPToInt: opt timing

src/main/scala/xiangshan/backend/decode/FPDecoder.scala

@@ -27,7 +27,7 @@ class FPDecoder extends XSModule{
     FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y),
     FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y),
     FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y),
-    FMV_X_W  -> List(N,s,X,N,N,N,N,N,N),
+    FMV_X_W  -> List(N,d,X,N,N,N,N,N,N),
     FCLASS_S -> List(N,s,X,N,N,N,N,N,N),
     FCVT_W_S -> List(N,s,X,N,Y,N,N,N,Y),
     FCVT_WU_S-> List(N,s,X,N,Y,N,N,N,Y),

src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala

@@ -18,30 +18,37 @@ class FPToInt extends FPUPipelineModule {
 
   val ctrl = io.in.bits.uop.ctrl.fpu
 
-  val src1_s = unbox(src1, S, Some(FType.S))
-  val src1_d = unbox(src1, ctrl.typeTagIn, None)
-  val src2_d = unbox(src2, ctrl.typeTagIn, None)
-
-  val src1_ieee = ieee(src1)
-  val move_out = Mux(ctrl.typeTagIn === S, src1_ieee(31, 0), src1_ieee)
+  // stage 1: unbox inputs
+  val src1_d = S1Reg(unbox(src1, ctrl.typeTagIn, None))
+  val src2_d = S1Reg(unbox(src2, ctrl.typeTagIn, None))
+  val ctrl_reg = S1Reg(ctrl)
+  val rm_reg = S1Reg(rm)
+
+  // stage2
+
+  val src1_ieee = ieee(src1_d)
+  val move_out = Mux(ctrl_reg.typeTagIn === S,
+    src1_ieee(FType.S.ieeeWidth - 1, 0),
+    src1_ieee
+  )
 
-  val classify_out = Mux(ctrl.typeTagIn === S,
-    FType.S.classify(src1_s),
-    FType.D.classify(src1)
+  val classify_out = Mux(ctrl_reg.typeTagIn === S,
+    FType.S.classify(maxType.unsafeConvert(src1_d, FType.S)),
+    FType.D.classify(src1_d)
   )
 
   val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
   dcmp.io.a := src1_d
   dcmp.io.b := src2_d
-  dcmp.io.signaling := !rm(1)
+  dcmp.io.signaling := !rm_reg(1)
 
-  val dcmp_out = ((~rm).asUInt() & Cat(dcmp.io.lt, dcmp.io.eq)).orR()
+  val dcmp_out = ((~rm_reg).asUInt() & Cat(dcmp.io.lt, dcmp.io.eq)).orR()
   val dcmp_exc = dcmp.io.exceptionFlags
 
   val conv = Module(new RecFNToIN(maxExpWidth, maxSigWidth, XLEN))
   conv.io.in := src1_d
-  conv.io.roundingMode := rm
-  conv.io.signedOut := ~ctrl.typ(0)
+  conv.io.roundingMode := rm_reg
+  conv.io.signedOut := ~ctrl_reg.typ(0)
 
   val conv_out = WireInit(conv.io.out)
   val conv_exc = WireInit(Cat(
@@ -52,10 +59,10 @@ class FPToInt extends FPUPipelineModule {
 
   val narrow = Module(new RecFNToIN(maxExpWidth, maxSigWidth, 32))
   narrow.io.in := src1_d
-  narrow.io.roundingMode := rm
-  narrow.io.signedOut := ~ctrl.typ(0)
+  narrow.io.roundingMode := rm_reg
+  narrow.io.signedOut := ~ctrl_reg.typ(0)
 
-  when(!ctrl.typ(1)) { // fcvt.w/wu.fp
+  when(!ctrl_reg.typ(1)) { // fcvt.w/wu.fp
     val excSign = src1_d(maxExpWidth + maxSigWidth) && !maxType.isNaN(src1_d)
     val excOut = Cat(conv.io.signedOut === excSign, Fill(32 - 1, !excSign))
     val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
@@ -67,26 +74,18 @@ class FPToInt extends FPUPipelineModule {
 
 
   val intData = Wire(UInt(XLEN.W))
-  intData := Mux(ctrl.wflags,
-    Mux(ctrl.fcvt, conv_out, dcmp_out),
-    Mux(rm(0), classify_out, move_out)
+  intData := Mux(ctrl_reg.wflags,
+    Mux(ctrl_reg.fcvt, conv_out, dcmp_out),
+    Mux(rm_reg(0), classify_out, move_out)
   )
-  val doubleOut = Mux(ctrl.fcvt, ctrl.typ(1), ctrl.fmt(0))
-  val intValue = Mux(doubleOut,
+  val doubleOut = Mux(ctrl_reg.fcvt, ctrl_reg.typ(1), ctrl_reg.fmt(0))
+  val intValue = S2Reg(Mux(doubleOut,
     SignExt(intData, XLEN),
     SignExt(intData(31, 0), XLEN)
-  )
-
-  val exc = Mux(ctrl.fcvt, conv_exc, dcmp_exc)
-
-  var dataVec = Seq(intValue)
-  var excVec = Seq(exc)
+  ))
 
-  for (i <- 1 to latency) {
-    dataVec = dataVec :+ PipelineReg(i)(dataVec(i - 1))
-    excVec = excVec :+ PipelineReg(i)(excVec(i - 1))
-  }
+  val exc = S2Reg(Mux(ctrl_reg.fcvt, conv_exc, dcmp_exc))
 
-  io.out.bits.data := dataVec.last
-  fflags := excVec.last
+  io.out.bits.data := intValue
+  fflags := exc
 }