utils,RegMap: support unwritable register

src/main/scala/device/AXI4UART.scala

@@ -40,12 +40,12 @@ class AXI4UART extends AXI4SlaveModule(new AXI4Lite) {
   val getcHelper = Module(new UARTGetc)
   getcHelper.io.clk := clock
   getcHelper.io.getc := (raddr(3,0) === 0.U && ren)
-  when (getcHelper.io.getc) { rxfifo := getcHelper.io.ch }
 
   def putc(c: UInt): UInt = { printf("%c", c(7,0)); c }
+  def getc = getcHelper.io.ch
 
   val mapping = Map(
-    RegMap(0x0, rxfifo),
+    RegMap(0x0, getc, RegMap.Unwritable),
     RegMap(0x4, txfifo, putc),
     RegMap(0x8, stat),
     RegMap(0xc, ctrl)

src/main/scala/utils/RegMap.scala

@@ -4,13 +4,14 @@ import chisel3._
 import chisel3.util._
 
 object RegMap {
+  def Unwritable = null
   def apply(addr: Int, reg: UInt, wfn: UInt => UInt = (x => x)) = (addr, (reg, wfn))
   def generate(mapping: Map[Int, (UInt, UInt => UInt)], raddr: UInt, rdata: UInt,
     waddr: UInt, wen: Bool, wdata: UInt, wmask: UInt):Unit = {
     val chiselMapping = mapping.map { case (a, (r, w)) => (a.U, r, w) }
     rdata := LookupTree(raddr, chiselMapping.map { case (a, r, w) => (a, r) })
-    when (wen) {
-      chiselMapping.map { case (a, r, w) => when (waddr === a) { r := w(MaskData(r, wdata, wmask)) } }
+    chiselMapping.map { case (a, r, w) =>
+      if (w != null) when (wen && waddr === a) { r := w(MaskData(r, wdata, wmask)) }
     }
   }
   def generate(mapping: Map[Int, (UInt, UInt => UInt)], addr: UInt, rdata: UInt,