busyTable: update read io

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -16,7 +16,7 @@ import xiangshan.mem.LsqEnqIO
 
 class CtrlToIntBlockIO extends XSBundle {
   val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp))
-  val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN)))
+  val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W)))
   val jumpPc = Output(UInt(VAddrBits.W))
   // int block only uses port 0~7
   val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here
@@ -25,7 +25,7 @@ class CtrlToIntBlockIO extends XSBundle {
 
 class CtrlToFpBlockIO extends XSBundle {
   val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp))
-  val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1)))
+  val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W)))
   // fp block uses port 0~11
   val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W)))
   val redirect = ValidIO(new Redirect)
@@ -131,10 +131,8 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
     setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen
     setPhyRegRdy.bits := wb.bits.uop.pdest
   }
-  intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr)
-  intBusyTable.io.pregRdy <> dispatch.io.intPregRdy
-  fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr)
-  fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy
+  intBusyTable.io.read <> dispatch.io.readIntState
+  fpBusyTable.io.read <> dispatch.io.readFpState
 
   roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid
   roq.io.redirect.bits <> redirectArb

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -152,7 +152,7 @@ class FloatBlock
 
 
   // read fp rf from ctrl block
-  fpRf.io.readPorts <> io.fromCtrlBlock.readRf
+  fpRf.io.readPorts.zipWithIndex.map{ case (r, i) => r.addr := io.fromCtrlBlock.readRf(i) }
   (0 until exuParameters.StuCnt).foreach(i => io.toMemBlock.readFpRf(i).data := fpRf.io.readPorts(i + 12).data)
   // write fp rf arbiter
   val fpWbArbiter = Module(new Wb(

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -218,7 +218,7 @@ class IntegerBlock
   jmpExeUnit.fenceio <> io.fenceio
 
   // read int rf from ctrl block
-  intRf.io.readPorts <> io.fromCtrlBlock.readRf
+  intRf.io.readPorts.zipWithIndex.map{ case(r, i) => r.addr := io.fromCtrlBlock.readRf(i) }
   (0 until NRMemReadPorts).foreach(i => io.toMemBlock.readIntRf(i).data := intRf.io.readPorts(i + 8).data)
   // write int rf arbiter
   val intWbArbiter = Module(new Wb(

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -7,7 +7,7 @@ import utils._
 import xiangshan.backend.regfile.RfReadPort
 import chisel3.ExcitingUtils._
 import xiangshan.backend.roq.{RoqPtr, RoqEnqIO}
-import xiangshan.backend.rename.RenameBypassInfo
+import xiangshan.backend.rename.{RenameBypassInfo, BusyTableReadIO}
 import xiangshan.mem.LsqEnqIO
 
 case class DispatchParameters
@@ -34,11 +34,11 @@ class Dispatch extends XSModule {
     // enq Lsq
     val enqLsq = Flipped(new LsqEnqIO)
     // read regfile
-    val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN)))
-    val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1)))
-    // read reg status (busy/ready)
-    val intPregRdy = Vec(NRIntReadPorts, Input(Bool()))
-    val fpPregRdy = Vec(NRFpReadPorts, Input(Bool()))
+    val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    // to busytable: read physical registers' state (busy/ready)
+    val readIntState= Vec(NRIntReadPorts, Flipped(new BusyTableReadIO))
+    val readFpState = Vec(NRFpReadPorts, Flipped(new BusyTableReadIO))
     // to reservation stations
     val numExist = Input(Vec(exuParameters.ExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))
@@ -82,7 +82,7 @@ class Dispatch extends XSModule {
   val intDispatch = Module(new Dispatch2Int)
   intDispatch.io.fromDq <> intDq.io.deq
   intDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i)})
-  intDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.intPregRdy(i)})
+  intDispatch.io.readState.zipWithIndex.map({case (r, i) => r <> io.readIntState(i)})
   intDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(i)})
   intDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i)})
 //  intDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i)})
@@ -92,7 +92,7 @@ class Dispatch extends XSModule {
   val fpDispatch = Module(new Dispatch2Fp)
   fpDispatch.io.fromDq <> fpDq.io.deq
   fpDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i)})
-  fpDispatch.io.regRdy.zipWithIndex.map({case (r, i) => r <> io.fpPregRdy(i)})
+  fpDispatch.io.readState.zipWithIndex.map({case (r, i) => r <> io.readFpState(i)})
   fpDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(i + exuParameters.IntExuCnt)})
   fpDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i + exuParameters.IntExuCnt)})
 //  fpDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i + exuParameters.IntExuCnt)})
@@ -103,8 +103,8 @@ class Dispatch extends XSModule {
   lsDispatch.io.fromDq <> lsDq.io.deq
   lsDispatch.io.readIntRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i + 8)})
   lsDispatch.io.readFpRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i + 12)})
-  lsDispatch.io.intRegRdy.zipWithIndex.map({case (r, i) => r <> io.intPregRdy(i + 8)})
-  lsDispatch.io.fpRegRdy.zipWithIndex.map({case (r, i) => r <> io.fpPregRdy(i + 12)})
+  lsDispatch.io.readIntState.zipWithIndex.map({case (r, i) => r <> io.readIntState(i + 8)})
+  lsDispatch.io.readFpState.zipWithIndex.map({case (r, i) => r <> io.readFpState(i + 12)})
   lsDispatch.io.numExist.zipWithIndex.map({case (num, i) => num := io.numExist(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
   lsDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
 //  lsDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -5,13 +5,14 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
+import xiangshan.backend.rename.BusyTableReadIO
 import xiangshan.backend.exu.Exu._
 
 class Dispatch2Fp extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp)))
-    val readRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new RfReadPort(XLEN + 1)))
-    val regRdy = Vec(NRFpReadPorts - exuParameters.StuCnt, Input(Bool()))
+    val readRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
+    val readState = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new BusyTableReadIO))
     val numExist = Input(Vec(exuParameters.FpExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp))
     val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W)))
@@ -51,9 +52,12 @@ class Dispatch2Fp extends XSModule {
   val fpDynamicMapped = fpDynamicIndex.map(i => indexVec(i))
   for (i <- fpStaticIndex.indices) {
     val index = WireInit(VecInit(fpStaticMapped(i) +: fpDynamicMapped))
-    io.readRf(3*i  ).addr := io.fromDq(index(fpReadPortSrc(i))).bits.psrc1
-    io.readRf(3*i+1).addr := io.fromDq(index(fpReadPortSrc(i))).bits.psrc2
-    io.readRf(3*i+2).addr := io.fromDq(index(fpReadPortSrc(i))).bits.psrc3
+    io.readRf(3*i  ) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc1
+    io.readRf(3*i+1) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc2
+    io.readRf(3*i+2) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc3
+    io.readState(3*i  ).req := io.fromDq(index(fpReadPortSrc(i))).bits.psrc1
+    io.readState(3*i+1).req := io.fromDq(index(fpReadPortSrc(i))).bits.psrc2
+    io.readState(3*i+2).req := io.fromDq(index(fpReadPortSrc(i))).bits.psrc3
   }
   val readPortIndex = Wire(Vec(exuParameters.FpExuCnt, UInt(2.W)))
   fpStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
@@ -74,9 +78,9 @@ class Dispatch2Fp extends XSModule {
     }
     enq.bits := io.fromDq(indexVec(i)).bits
     
-    val src1Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3)))
-    val src2Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3 + 1)))
-    val src3Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3 + 2)))
+    val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 3).resp))
+    val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 1).resp))
+    val src3Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 2).resp))
     enq.bits.src1State := src1Ready(readPortIndex(i))
     enq.bits.src2State := src2Ready(readPortIndex(i))
     enq.bits.src3State := src3Ready(readPortIndex(i))

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -6,12 +6,13 @@ import xiangshan._
 import utils._
 import xiangshan.backend.exu.Exu._
 import xiangshan.backend.regfile.RfReadPort
+import xiangshan.backend.rename.BusyTableReadIO
 
 class Dispatch2Int extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)))
-    val readRf = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new RfReadPort(XLEN)))
-    val regRdy = Vec(NRIntReadPorts - NRMemReadPorts, Input(Bool()))
+    val readRf = Vec(NRIntReadPorts - NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    val readState = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new BusyTableReadIO))
     val numExist = Input(Vec(exuParameters.IntExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp))
     val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W)))
@@ -58,8 +59,10 @@ class Dispatch2Int extends XSModule {
   val intDynamicMapped = intDynamicIndex.map(i => indexVec(i))
   for (i <- intStaticIndex.indices) {
     val index = WireInit(VecInit(intStaticMapped(i) +: intDynamicMapped))
-    io.readRf(2*i  ).addr := io.fromDq(index(intReadPortSrc(i))).bits.psrc1
-    io.readRf(2*i+1).addr := io.fromDq(index(intReadPortSrc(i))).bits.psrc2
+    io.readRf(2*i  ) := io.fromDq(index(intReadPortSrc(i))).bits.psrc1
+    io.readRf(2*i+1) := io.fromDq(index(intReadPortSrc(i))).bits.psrc2
+    io.readState(2*i  ).req := io.fromDq(index(intReadPortSrc(i))).bits.psrc1
+    io.readState(2*i+1).req := io.fromDq(index(intReadPortSrc(i))).bits.psrc2
   }
   val readPortIndex = Wire(Vec(exuParameters.IntExuCnt, UInt(2.W)))
   intStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
@@ -84,8 +87,8 @@ class Dispatch2Int extends XSModule {
     }
     enq.bits := io.fromDq(indexVec(i)).bits
     
-    val src1Ready = VecInit((0 until 4).map(i => io.regRdy(i * 2)))
-    val src2Ready = VecInit((0 until 4).map(i => io.regRdy(i * 2 + 1)))
+    val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 2).resp))
+    val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 2 + 1).resp))
     enq.bits.src1State := src1Ready(readPortIndex(i))
     enq.bits.src2State := src2Ready(readPortIndex(i))
 

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -5,17 +5,18 @@ import chisel3.util._
 import xiangshan._
 import utils._
 import xiangshan.backend.regfile.RfReadPort
+import xiangshan.backend.rename.BusyTableReadIO
 import xiangshan.backend.exu.Exu._
 
 class Dispatch2Ls extends XSModule {
   val io = IO(new Bundle() {
     val fromDq = Flipped(Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)))
-    val readIntRf = Vec(NRMemReadPorts, Flipped(new RfReadPort(XLEN)))
-    val readFpRf = Vec(exuParameters.StuCnt, Flipped(new RfReadPort(XLEN + 1)))
+    val readIntRf = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    val readFpRf = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
     // val intRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
     // val fpRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
-    val intRegRdy = Vec(NRMemReadPorts, Input(Bool()))
-    val fpRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
+    val readIntState = Vec(NRMemReadPorts, Flipped(new BusyTableReadIO))
+    val readFpState = Vec(exuParameters.StuCnt, Flipped(new BusyTableReadIO))
     val numExist = Input(Vec(exuParameters.LsExuCnt, UInt(log2Ceil(IssQueSize).W)))
     val enqIQCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp))
   })
@@ -52,12 +53,16 @@ class Dispatch2Ls extends XSModule {
   val readPort = Seq(0, 1, 2, 4)
   for (i <- 0 until exuParameters.LsExuCnt) {
     if (i < exuParameters.LduCnt) {
-      io.readIntRf(readPort(i)).addr := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntRf(readPort(i)) := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntState(readPort(i)).req := io.fromDq(indexVec(i)).bits.psrc1
     }
     else {
-      io.readFpRf(i - exuParameters.LduCnt).addr := io.fromDq(indexVec(i)).bits.psrc2
-      io.readIntRf(readPort(i)  ).addr := io.fromDq(indexVec(i)).bits.psrc1
-      io.readIntRf(readPort(i)+1).addr := io.fromDq(indexVec(i)).bits.psrc2
+      io.readFpRf(i - exuParameters.LduCnt) := io.fromDq(indexVec(i)).bits.psrc2
+      io.readIntRf(readPort(i)  ) := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntRf(readPort(i)+1) := io.fromDq(indexVec(i)).bits.psrc2
+      io.readFpState(i - exuParameters.LduCnt).req := io.fromDq(indexVec(i)).bits.psrc2
+      io.readIntState(readPort(i)  ).req := io.fromDq(indexVec(i)).bits.psrc1
+      io.readIntState(readPort(i)+1).req := io.fromDq(indexVec(i)).bits.psrc2
     }
   }
 
@@ -75,13 +80,13 @@ class Dispatch2Ls extends XSModule {
       enq.valid := storeIndexGen.io.mapping(i - exuParameters.LduCnt).valid && storeReady
     }
     enq.bits := io.fromDq(indexVec(i)).bits
-    enq.bits.src1State := io.intRegRdy(readPort(i))
+    enq.bits.src1State := io.readIntState(readPort(i)).resp
     if (i < exuParameters.LduCnt) {
       enq.bits.src2State := DontCare
     }
     else {
       enq.bits.src2State := Mux(io.fromDq(indexVec(i)).bits.ctrl.src2Type === SrcType.fp,
-        io.fpRegRdy(i - exuParameters.LduCnt), io.intRegRdy(readPort(i) + 1))
+        io.readFpState(i - exuParameters.LduCnt).resp, io.readIntState(readPort(i) + 1).resp)
     }
 
     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +

src/main/scala/xiangshan/backend/rename/BusyTable.scala

@@ -5,6 +5,11 @@ import chisel3.util._
 import xiangshan._
 import utils.{ParallelOR, XSDebug}
 
+class BusyTableReadIO extends XSBundle {
+  val req = Input(UInt(PhyRegIdxWidth.W))
+  val resp = Output(Bool())
+}
+
 class BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule {
   val io = IO(new Bundle() {
     val flush = Input(Bool())
@@ -13,8 +18,7 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule {
     // set preg state to ready (write back regfile + roq walk)
     val wbPregs = Vec(numWritePorts, Flipped(ValidIO(UInt(PhyRegIdxWidth.W))))
     // read preg state
-    val rfReadAddr = Vec(numReadPorts, Input(UInt(PhyRegIdxWidth.W)))
-    val pregRdy = Vec(numReadPorts, Output(Bool()))
+    val read = Vec(numReadPorts, new BusyTableReadIO)
   })
 
   val table = RegInit(0.U(NRPhyRegs.W))
@@ -29,27 +33,10 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int) extends XSModule {
   val tableAfterWb = table & (~wbMask).asUInt
   val tableAfterAlloc = tableAfterWb | allocMask
 
-  for((raddr, rdy) <- io.rfReadAddr.zip(io.pregRdy)){
-    rdy := !tableAfterWb(raddr)
-  }
+  io.read.map(r => r.resp := !tableAfterWb(r.req))
 
   table := tableAfterAlloc
 
-//  for((alloc, i) <- io.allocPregs.zipWithIndex){
-//    when(alloc.valid){
-//      table(alloc.bits) := true.B
-//    }
-//    XSDebug(alloc.valid, "Allocate %d\n", alloc.bits)
-//  }
-
-
-//  for((wb, i) <- io.wbPregs.zipWithIndex){
-//    when(wb.valid){
-//      table(wb.bits) := false.B
-//    }
-//    XSDebug(wb.valid, "writeback %d\n", wb.bits)
-//  }
-
   when(io.flush){
     table := 0.U(NRPhyRegs.W)
   }