fix: fix bugs in FMA and Rab

src/main/scala/xiangshan/backend/fu/fpu/FMA.scala

@@ -186,7 +186,7 @@ class FMA(cfg: FuConfig)(implicit p: Parameters) extends FPUSubModule(cfg) {
   val isFMA = mul_pipe.io.out.valid && mul_pipe.io.out.bits.ctrl.fpu.get.ren3
   // However, when sending instructions to add_pipe, we need to determine whether it's flushed.
   val mulFlushed = mul_pipe.io.out.bits.ctrl.robIdx.needFlush(io.flush)
-  val isFMAReg = RegNext(isFMA && !mulFlushed)
+  val isFMAReg = isFMA && !mulFlushed
 
   add_pipe.mulToAdd <> mul_pipe.toAdd
 

src/main/scala/xiangshan/backend/rob/Rab.scala

@@ -62,7 +62,7 @@ class RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasC
   val headPtrOHShift = CircularShift(headPtrOH)
   // may shift [0, CommitWidth] steps
   val headPtrOHVec = VecInit.tabulate(CommitWidth + 1)(headPtrOHShift.left)
-  val headPtrOHVec2 = VecInit.tabulate(CommitWidth * MaxUopSize + 1)(headPtrOHShift.left)
+  val headPtrOHVec2 = VecInit(Seq.tabulate(CommitWidth * MaxUopSize + 1)(_ % size).map(step => headPtrOHShift.left(step)))
 
   val vcfgPtrOH = RegInit(1.U(size.W))
   val vcfgPtrOHShift = CircularShift(vcfgPtrOH)
@@ -72,7 +72,7 @@ class RenameBuffer(size: Int)(implicit p: Parameters) extends XSModule with HasC
   val diffPtrOH = RegInit(1.U(size.W))
   val diffPtrOHShift = CircularShift(diffPtrOH)
   // may shift [0, CommitWidth * MaxUopSize] steps
-  val diffPtrOHVec = VecInit.tabulate(CommitWidth * MaxUopSize + 1)(diffPtrOHShift.left)
+  val diffPtrOHVec = VecInit(Seq.tabulate(CommitWidth * MaxUopSize + 1)(_ % size).map(step => diffPtrOHShift.left(step)))
 
   val tailPtr = RegInit(RenameBufferPtr(false, 0))
   val tailPtrOH = RegInit(1.U(size.W))