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提交 b2e234eb 编写于 作者: L LinJiawei
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CSR,Jump: move to new function unit, fix syntax bugs

上级 3142d695
隐藏空白更改
内联 并排
Showing with 92 addition and 63 deletion
src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala
浏览文件 @ b2e234eb
......@@ -21,17 +21,23 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
jmp.io.in.valid := io.in.valid && isJmp
jmp.io.in.bits := io.in.bits
jmp.io.out.ready := io.out.ready
jmp.io.exception <> DontCare
jmp.io.dmem <> DontCare
jmp.io.mcommit := DontCare
jmp.io.redirect := io.redirect
jmp.io.redirectIn := io.redirect
val jumpExuOut = Wire(new ExuOutput)
val jumpExtraOut = jmp.io.out.bits.ext.get
jumpExuOut.uop := uop
jumpExuOut.data := jmp.io.out.bits.data
jumpExuOut.brUpdate := jumpExtraOut.brUpdate
jumpExuOut.redirect := jumpExtraOut.redirect
jumpExuOut.redirectValid := jumpExtraOut.redirectValid
jumpExuOut.debug := DontCare
csr.io.cfIn := io.in.bits.uop.cf
csr.io.fpu_csr := DontCare
csr.io.exception <> io.exception
csr.io.instrValid := DontCare
csr.io.out.ready := io.out.ready
csr.io.in.bits.src3 := DontCare
val csrOut = csr.access(
valid = io.in.valid && fuType === FuType.csr,
src1 = io.in.bits.src1,
......@@ -44,14 +50,14 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
csrExuOut.uop.cf := csr.io.cfOut
csrExuOut.uop.ctrl.flushPipe := csr.io.flushPipe
csrExuOut.data := csrOut
csrExuOut.redirectValid := csr.io.redirectValid
csrExuOut.redirectValid := csr.io.redirectOutValid
csrExuOut.redirect.brTag := uop.brTag
csrExuOut.redirect.isException := false.B
csrExuOut.redirect.isMisPred := false.B
csrExuOut.redirect.isFlushPipe := false.B
csrExuOut.redirect.isReplay := false.B
csrExuOut.redirect.roqIdx := uop.roqIdx
csrExuOut.redirect.target := csr.io.redirect.target
csrExuOut.redirect.target := csr.io.redirectOut.target
csrExuOut.redirect.pc := uop.cf.pc
csrExuOut.debug := DontCare
csrExuOut.brUpdate := DontCare
......@@ -66,7 +72,13 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
// NOTE: just one instr in this module at the same time
io.in.ready := jmp.io.in.ready && csr.io.in.ready && fence.io.in.ready
io.out.bits := Mux(jmp.io.out.valid, jmp.io.out.bits, Mux(csr.io.out.valid, csrExuOut, fence.io.out.bits))
io.out.bits := Mux(jmp.io.out.valid,
jumpExuOut,
Mux(csr.io.out.valid,
csrExuOut,
fence.io.out.bits
)
)
io.out.valid := jmp.io.out.valid || csr.io.out.valid || fence.io.out.valid
XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready} ${jmp.io.in.ready}${csr.io.in.ready}${fence.io.in.ready}) pc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} roqIdx:${io.in.bits.uop.roqIdx} fuType:b${Binary(io.in.bits.uop.ctrl.fuType)} fuOpType:b${Binary(io.in.bits.uop.ctrl.fuOpType)} isJmp:${isJmp} isCsr${isCsr} isFence:${isFence}\n")
......
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @ b2e234eb
......@@ -53,11 +53,11 @@ trait HasCSRConst {
// Supervisor Protection and Translation
val Satp = 0x180
// Machine Information Registers
val Mvendorid = 0xF11
val Marchid = 0xF12
val Mimpid = 0xF13
val Mhartid = 0xF14
// Machine Information Registers
val Mvendorid = 0xF11
val Marchid = 0xF12
val Mimpid = 0xF13
val Mhartid = 0xF14
// Machine Trap Setup
val Mstatus = 0x300
......@@ -84,7 +84,7 @@ trait HasCSRConst {
val PmpaddrBase = 0x3B0
// Machine Counter/Timers
// Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers
// Currently, we uses perfcnt csr set instead of standard Machine Counter/Timers
// 0xB80 - 0x89F are also used as perfcnt csr
// Machine Counter Setup (not implemented)
......@@ -166,10 +166,11 @@ class FpuCsrIO extends XSBundle {
val frm = Input(UInt(3.W))
}
class CSRIO extends FunctionUnitIO {
class CSRIO extends FunctionUnitIO[UInt, Null](csrCfg, 64, FuOpType()) {
val cfIn = Input(new CtrlFlow)
val redirect = Output(new Redirect)
val redirectValid = Output(Bool())
val redirectOut = Output(new Redirect)
val redirectOutValid = Output(Bool())
val fpu_csr = Flipped(new FpuCsrIO)
val cfOut = Output(new CtrlFlow)
// from rob
......@@ -182,18 +183,23 @@ class CSRIO extends FunctionUnitIO {
val wenFix = Output(Bool())
}
class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val io = IO(new CSRIO)
class CSR extends FunctionUnit[UInt, Null](csrCfg, 64, FuOpType())
with HasCSRConst
{
override val io = new CSRIO
io.cfOut := io.cfIn
val (valid, src1, src2, func) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.func)
val (valid, src1, src2, func) =
(io.in.valid, io.in.bits.src(0), io.in.bits.src(1), io.in.bits.ext.get)
def access(valid: Bool, src1: UInt, src2: UInt, func: UInt): UInt = {
this.valid := valid
this.src1 := src1
this.src2 := src2
this.func := func
io.out.bits
io.out.bits.data
}
// CSR define
......@@ -257,14 +263,14 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val mipFixMask = GenMask(9) | GenMask(5) | GenMask(1)
val mip = (mipWire.asUInt | mipReg).asTypeOf(new Interrupt)
def getMisaMxl(mxl: Int): UInt = {mxl.U << (XLEN-2)}
def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)}
def getMisaMxl(mxl: Int): UInt = {mxl.U << (XLEN-2)}.asUInt()
def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)}.asUInt()
var extList = List('a', 's', 'i', 'u')
if(HasMExtension){ extList = extList :+ 'm'}
if(HasCExtension){ extList = extList :+ 'c'}
if(HasFPU){ extList = extList ++ List('f', 'd')}
val misaInitVal = getMisaMxl(2) | extList.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
val misa = RegInit(UInt(XLEN.W), misaInitVal)
val misaInitVal = getMisaMxl(2) | extList.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) //"h8000000000141105".U
val misa = RegInit(UInt(XLEN.W), misaInitVal)
// MXL = 2 | 0 | EXT = b 00 0000 0100 0001 0001 0000 0101
// (XLEN-1, XLEN-2) | |(25, 0) ZY XWVU TSRQ PONM LKJI HGFE DCBA
......@@ -300,12 +306,12 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
mstatusNew
}
val mstatusMask = ~ZeroExt((
val mstatusMask = (~ZeroExt((
GenMask(XLEN-2, 38) | GenMask(31, 23) | GenMask(10, 9) | GenMask(2) |
GenMask(37) | // MBE
GenMask(36) | // SBE
GenMask(6) // UBE
), 64)
), 64)).asUInt()
val medeleg = RegInit(UInt(XLEN.W), 0.U)
val mideleg = RegInit(UInt(XLEN.W), 0.U)
......@@ -338,7 +344,7 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val sipMask = "h222".U & mideleg
val satp = RegInit(0.U(XLEN.W))
// val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
val satpMask = "h80000fffffffffff".U // disable asid, mode can only be 8 / 0
val satpMask = "h80000fffffffffff".U // disable asid, mode can only be 8 / 0
// val satp = RegInit(UInt(XLEN.W), 0.U)
val sepc = RegInit(UInt(XLEN.W), 0.U)
val scause = RegInit(UInt(XLEN.W), 0.U)
......@@ -511,11 +517,11 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
))
// satp wen check
val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
val satpLegalMode = (wdata.asTypeOf(new SatpStruct).mode===0.U) || (wdata.asTypeOf(new SatpStruct).mode===8.U)
// general CSR wen check
val wen = valid && func =/= CSROpType.jmp && (addr=/=Satp.U || satpLegalMode)
val permitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode)
val permitted = csrAccessPermissionCheck(addr, false.B, priviledgeMode)
// Writeable check is ingored.
// Currently, write to illegal csr addr will be ignored
MaskedRegMap.generate(mapping, addr, rdata, wen && permitted, wdata)
......@@ -676,12 +682,12 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
val trapTarget = Wire(UInt(VAddrBits.W))
ExcitingUtils.addSource(trapTarget, "trapTarget")
val resetSatp = addr === Satp.U && wen // write to satp will cause the pipeline be flushed
io.redirect := DontCare
io.redirectValid := valid && func === CSROpType.jmp && !isEcall
io.redirect.target := retTarget
io.redirectOut := DontCare
io.redirectOutValid := valid && func === CSROpType.jmp && !isEcall
io.redirectOut.target := retTarget
io.flushPipe := resetSatp
XSDebug(io.redirectValid, "redirect to %x, pc=%x\n", io.redirect.target, io.cfIn.pc)
XSDebug(io.redirectOutValid, "redirect to %x, pc=%x\n", io.redirectOut.target, io.cfIn.pc)
XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",io.exception.bits.cf.pc, intrNO, io.exception.bits.cf.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
XSDebug(raiseExceptionIntr, "pc %x mstatus %x mideleg %x medeleg %x mode %x\n", io.exception.bits.cf.pc, mstatus, mideleg, medeleg, priviledgeMode)
......@@ -765,10 +771,10 @@ class CSR extends FunctionUnit(csrCfg) with HasCSRConst{
io.out.valid := valid
XSDebug(io.redirectValid, "Rediret %x raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d deleg:%x cfInpc:%x valid:%d instrValid:%x \n",
io.redirect.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
XSDebug(io.redirectOutValid, "Rediret %x raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d deleg:%x cfInpc:%x valid:%d instrValid:%x \n",
io.redirectOut.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
XSDebug(raiseExceptionIntr && delegS, "Red(%d, %x) raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d deleg:%x cfInpc:%x valid:%d instrValid:%x \n",
io.redirectValid, io.redirect.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
io.redirectOutValid, io.redirectOut.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
XSDebug(raiseExceptionIntr && delegS, "sepc is writen!!! pc:%x\n", io.cfIn.pc)
......
src/main/scala/xiangshan/backend/fu/Jump.scala
浏览文件 @ b2e234eb
......@@ -8,34 +8,48 @@ import xiangshan.backend._
import xiangshan.backend.fu.FunctionUnit._
import xiangshan.backend.decode.isa._
class Jump extends FunctionUnit(jmpCfg){
val io = IO(new ExuIO)
class RedirectOut extends XSBundle {
val redirectValid = Bool()
val redirect = new Redirect
val brUpdate = new BranchUpdateInfo
}
class Jump extends FunctionUnit(jmpCfg, extOut = new RedirectOut) {
val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
val (iovalid, src1, offset, func, pc, uop) = (
io.in.valid,
io.in.bits.src(0),
io.in.bits.uop.ctrl.imm,
io.in.bits.uop.ctrl.fuOpType,
SignExt(io.in.bits.uop.cf.pc, AddrBits),
io.in.bits.uop
)
val redirectHit = uop.needFlush(io.redirect)
val redirectHit = uop.needFlush(io.redirectIn)
val valid = iovalid && !redirectHit
val isRVC = uop.cf.brUpdate.pd.isRVC
val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
io.out.bits.redirectValid := valid
io.out.bits.redirect.pc := uop.cf.pc
io.out.bits.redirect.target := target
io.out.bits.redirect.brTag := uop.brTag
io.out.bits.redirect.isException := false.B
io.out.bits.redirect.isFlushPipe := false.B
io.out.bits.redirect.isMisPred := DontCare // check this in brq
io.out.bits.redirect.isReplay := false.B
io.out.bits.redirect.roqIdx := uop.roqIdx
val redirectOut = io.out.bits.ext.get.redirect
val brUpdate = io.out.bits.ext.get.brUpdate
io.out.bits.ext.get.redirectValid := valid
redirectOut.pc := uop.cf.pc
redirectOut.target := target
redirectOut.brTag := uop.brTag
redirectOut.isException := false.B
redirectOut.isFlushPipe := false.B
redirectOut.isMisPred := DontCare // check this in brq
redirectOut.isReplay := false.B
redirectOut.roqIdx := uop.roqIdx
io.out.bits.brUpdate := uop.cf.brUpdate
io.out.bits.brUpdate.pc := uop.cf.pc
io.out.bits.brUpdate.target := target
io.out.bits.brUpdate.brTarget := target // DontCare
// io.out.bits.brUpdate.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
io.out.bits.brUpdate.taken := true.B
brUpdate := uop.cf.brUpdate
brUpdate.pc := uop.cf.pc
brUpdate.target := target
brUpdate.brTarget := target // DontCare
brUpdate.taken := true.B
// io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U //TODO: consider RVC
// Output
......@@ -46,20 +60,17 @@ class Jump extends FunctionUnit(jmpCfg){
io.out.bits.uop <> io.in.bits.uop
io.out.bits.data := res
io.dmem <> DontCare
io.out.bits.debug <> DontCare
// NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d %d) brTag:%x\n",
io.in.valid,
io.in.ready,
io.out.valid,
io.out.ready,
io.redirect.valid,
io.redirect.bits.isException,
io.redirect.bits.isFlushPipe,
io.redirectIn.valid,
io.redirectIn.bits.isException,
io.redirectIn.bits.isFlushPipe,
redirectHit,
io.redirect.bits.brTag.value
io.redirectIn.bits.brTag.value
)
XSDebug(io.in.valid, "src1:%x offset:%x func:%b type:JUMP pc:%x res:%x\n", src1, offset, func, pc, res)
}
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