backend,mem: fix feedback signals of load

src/main/scala/xiangshan/Bundle.scala

@@ -83,7 +83,7 @@ object RSFeedbackType {
   }
 
   def isBlocked(feedbackType: UInt) = {
-    feedbackType === rfArbitFail || feedbackType === fuBusy || feedbackType === feedbackInvalid
+    feedbackType === rfArbitFail || feedbackType === fuBusy || feedbackType >= lrqFull && feedbackType <= feedbackInvalid
   }
 }
 

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -520,7 +520,7 @@ class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Paramet
     statusArray.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) =>
       fastResp.valid                 := memIO.feedbackIO(i).feedbackFast.valid
       fastResp.bits.addrOH           := UIntToOH(memIO.feedbackIO(i).feedbackFast.bits.rsIdx)
-      fastResp.bits.success          := false.B
+      fastResp.bits.success          := memIO.feedbackIO(i).feedbackFast.bits.hit
       fastResp.bits.respType         := memIO.feedbackIO(i).feedbackFast.bits.sourceType
       fastResp.bits.dataInvalidSqIdx := 0.U.asTypeOf(fastResp.bits.dataInvalidSqIdx)
     }

src/main/scala/xiangshan/backend/issue/StatusArray.scala

@@ -202,9 +202,15 @@ class StatusArray()(implicit p: Parameters, params: IssueBlockParams) extends XS
 class StatusArrayMem()(implicit p: Parameters, params: IssueBlockParams) extends StatusArray
   with HasCircularQueuePtrHelper {
 
+  private val needMemFeedback = params.StaCnt > 0 || params.LduCnt > 0
+
   val fromMem = io.fromMem.get
 
-  val memResps = resps ++ io.fromMem.get.slowResp ++ io.fromMem.get.fastResp
+  var memResps = resps
+  if (needMemFeedback) {
+    memResps ++= io.fromMem.get.slowResp
+    memResps ++= io.fromMem.get.fastResp
+  }
   deqRespVec.zipWithIndex.foreach { case (deqResp, i) =>
     val deqRespValidVec = VecInit(memResps.map(x => x.valid && x.bits.addrOH(i)))
     XSError(PopCount(deqRespValidVec) > 1.U, p"mem status deq resp ${Binary(deqRespValidVec.asUInt)} should be one-hot)\n")
@@ -216,7 +222,7 @@ class StatusArrayMem()(implicit p: Parameters, params: IssueBlockParams) extends
     val clearByFlush = (enqStatusVec(i).valid || validVec(i)) && flushedVec(i)
     val clearByResp = deqRespVec(i).valid && (
       //do: special mem success
-      if(params.StaCnt == 0) {
+      if(!needMemFeedback) {
         deqRespVec(i).bits.respType === RSFeedbackType.fuIdle
       }
       else{

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -117,6 +117,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
   val s0_mask = Wire(UInt(8.W))
   val s0_uop = Wire(new DynInst)
   val s0_isFirstIssue = Wire(Bool())
+  val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W))
   val s0_sqIdx = Wire(new SqPtr)
   val s0_tryFastpath = WireInit(false.B)
   val s0_replayCarry = Wire(new ReplayCarry) // way info for way predict related logic
@@ -255,6 +256,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
     s0_mask := genWmask(io.replay.bits.vaddr, io.replay.bits.uop.fuOpType(1, 0))
     s0_uop := io.replay.bits.uop
     s0_isFirstIssue := io.replay.bits.isFirstIssue
+    s0_rsIdx := io.replay.bits.rsIdx
     s0_sqIdx := io.replay.bits.uop.sqIdx
     s0_replayCarry := io.replay.bits.replayCarry
     val replayUopIsPrefetch = WireInit(LSUOpType.isPrefetch(io.replay.bits.uop.fuOpType))
@@ -267,6 +269,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
     s0_mask := 0.U
     s0_uop := DontCare
     s0_isFirstIssue := false.B
+    s0_rsIdx := DontCare
     s0_sqIdx := DontCare
     s0_replayCarry := DontCare
     // ctrl signal
@@ -279,6 +282,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
     s0_mask := genWmask(s0_vaddr, io.in.bits.uop.fuOpType(1,0))
     s0_uop := io.in.bits.uop
     s0_isFirstIssue := true.B
+    s0_rsIdx := io.in.bits.iqIdx
     s0_sqIdx := io.in.bits.uop.sqIdx
     val issueUopIsPrefetch = WireInit(LSUOpType.isPrefetch(io.in.bits.uop.fuOpType))
     when (issueUopIsPrefetch) {
@@ -295,6 +299,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
       // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing
       // because these signals will be updated in S1
       s0_isFirstIssue := true.B
+      s0_rsIdx := DontCare
       s0_sqIdx := DontCare
     }
   }
@@ -316,6 +321,7 @@ class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParamet
   io.out.bits.mask := s0_mask
   io.out.bits.uop := s0_uop
   io.out.bits.uop.exceptionVec(loadAddrMisaligned) := !addrAligned
+  io.out.bits.rsIdx := s0_rsIdx
   io.out.bits.isFirstIssue := s0_isFirstIssue
   io.out.bits.isPrefetch := isPrefetch
   io.out.bits.isHWPrefetch := isHWPrefetch
@@ -847,6 +853,10 @@ class LoadUnit(implicit p: Parameters) extends XSModule
   val load_s1 = Module(new LoadUnit_S1)
   val load_s2 = Module(new LoadUnit_S2)
 
+  dontTouch(load_s0.io)
+  dontTouch(load_s1.io)
+  dontTouch(load_s2.io)
+
   // load s0
   load_s0.io.in <> io.loadIn
   load_s0.io.dtlbReq <> io.tlb.req