LoadQueueData: wrap data in LQData8Module

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -17,8 +17,8 @@ class ExceptionAddrIO extends XSBundle {
 }
 
 class FwdEntry extends XSBundle {
-  val mask = Vec(8, Bool())
-  val data = Vec(8, UInt(8.W))
+  val valid = Bool()
+  val data = UInt(8.W)
 }
 
 // inflight miss block reqs

src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala

@@ -20,7 +20,7 @@ class LQDataEntry extends XSBundle {
 
 // Data module define
 // These data modules are like SyncDataModuleTemplate, but support cam-like ops
-class PaddrModule(numEntries: Int, numRead: Int, numWrite: Int) extends XSModule with HasDCacheParameters {
+class LQPaddrModule(numEntries: Int, numRead: Int, numWrite: Int) extends XSModule with HasDCacheParameters {
   val io = IO(new Bundle {
     val raddr = Input(Vec(numRead, UInt(log2Up(numEntries).W)))
     val rdata = Output(Vec(numRead, UInt((PAddrBits).W)))
@@ -106,7 +106,7 @@ class MaskModule(numEntries: Int, numRead: Int, numWrite: Int) extends XSModule
   }
 }
 
-class Data8Module(numEntries: Int, numRead: Int, numWrite: Int) extends XSModule with HasDCacheParameters {
+class LQData8Module(numEntries: Int, numRead: Int, numWrite: Int) extends XSModule with HasDCacheParameters {
   val io = IO(new Bundle {
     // read
     val raddr = Input(Vec(numRead, UInt(log2Up(numEntries).W)))
@@ -177,7 +177,7 @@ class CoredataModule(numEntries: Int, numRead: Int, numWrite: Int) extends XSMod
     val paddrWen = Input(Vec(numWrite, Bool()))
   })
 
-  val data8 = Seq.fill(8)(Module(new Data8Module(numEntries, numRead, numWrite)))
+  val data8 = Seq.fill(8)(Module(new LQData8Module(numEntries, numRead, numWrite)))
   val fwdMask = Reg(Vec(numEntries, UInt(8.W)))
   val wordIndex = Reg(Vec(numEntries, UInt((blockOffBits - wordOffBits).W)))
 
@@ -287,7 +287,7 @@ class LoadQueueData(size: Int, wbNumRead: Int, wbNumWrite: Int) extends XSModule
 
   // val data = Reg(Vec(size, new LQDataEntry))
   // data module
-  val paddrModule = Module(new PaddrModule(size, numRead = 3, numWrite = 2))
+  val paddrModule = Module(new LQPaddrModule(size, numRead = 3, numWrite = 2))
   val maskModule = Module(new MaskModule(size, numRead = 3, numWrite = 2))
   val coredataModule = Module(new CoredataModule(size, numRead = 3, numWrite = 3))
 

src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala

@@ -53,29 +53,28 @@ class SQPaddrModule(numEntries: Int, numRead: Int, numWrite: Int, numForward: In
   }
 }
 
-class SQDataEntry extends XSBundle {
+class SQData8Entry extends XSBundle {
   // val paddr = UInt(PAddrBits.W)
-  val mask = UInt(8.W)
-  val data = UInt(XLEN.W)
+  val valid = Bool()
+  val data = UInt((XLEN/8).W)
 }
 
-class StoreQueueData(size: Int, numRead: Int, numWrite: Int, numForward: Int) extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
+class SQData8Module(size: Int, numRead: Int, numWrite: Int, numForward: Int) extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val raddr = Vec(numRead,  Input(UInt(log2Up(size).W)))
-    val rdata = Vec(numRead,  Output(new SQDataEntry))
+    val rdata = Vec(numRead,  Output(new SQData8Entry))
     val wen   = Vec(numWrite, Input(Bool()))
     val waddr = Vec(numWrite, Input(UInt(log2Up(size).W)))
-    val wdata = Vec(numWrite, Input(new SQDataEntry))
-    val debug = Vec(size, Output(new SQDataEntry))
+    val wdata = Vec(numWrite, Input(new SQData8Entry))
 
     val needForward = Input(Vec(numForward, Vec(2, UInt(size.W))))
-    val forwardMask = Vec(numForward, Output(Vec(8, Bool())))
-    val forwardData = Vec(numForward, Output(Vec(8, UInt(8.W))))
+    val forwardValid = Vec(numForward, Output(Bool()))
+    val forwardData = Vec(numForward, Output(UInt(8.W)))
   })
 
   io := DontCare
 
-  val data = Reg(Vec(size, new SQDataEntry))
+  val data = Reg(Vec(size, new SQData8Entry))
 
   // writeback to lq/sq
   (0 until numWrite).map(i => {
@@ -115,10 +114,8 @@ class StoreQueueData(size: Int, numRead: Int, numWrite: Int, numForward: Int) ex
         val l = a.asTypeOf(new FwdEntry)
         val r = b.asTypeOf(new FwdEntry)
         val res = Wire(new FwdEntry)
-        (0 until 8).map(p => {
-          res.mask(p) := l.mask(p) || r.mask(p)
-          res.data(p) := Mux(r.mask(p), r.data(p), l.data(p))
-        })
+        res.valid := l.valid || r.valid
+        res.data := Mux(r.valid, r.data, l.data)
         res
       })
     }
@@ -132,19 +129,75 @@ class StoreQueueData(size: Int, numRead: Int, numWrite: Int, numForward: Int) ex
       val needCheck0 = RegNext(io.needForward(i)(0)(j))
       val needCheck1 = RegNext(io.needForward(i)(1)(j))
       (0 until XLEN / 8).foreach(k => {
-        matchResultVec(j).mask(k) := needCheck0 && data(j).mask(k)
-        matchResultVec(j).data(k) := data(j).data(8 * (k + 1) - 1, 8 * k)
-        matchResultVec(size + j).mask(k) := needCheck1 && data(j).mask(k)
-        matchResultVec(size + j).data(k) := data(j).data(8 * (k + 1) - 1, 8 * k)
+        matchResultVec(j).valid := needCheck0 && data(j).valid
+        matchResultVec(j).data := data(j).data
+        matchResultVec(size + j).valid := needCheck1 && data(j).valid
+        matchResultVec(size + j).data := data(j).data
       })
     }
 
     val parallelFwdResult = parallelFwd(matchResultVec).asTypeOf(new FwdEntry)
 
-    io.forwardMask(i) := parallelFwdResult.mask
+    io.forwardValid(i) := parallelFwdResult.valid
     io.forwardData(i) := parallelFwdResult.data
 
   })
+}
+
+class SQDataEntry extends XSBundle {
+  // val paddr = UInt(PAddrBits.W)
+  val mask = UInt(8.W)
+  val data = UInt(XLEN.W)
+}
+
+class StoreQueueData(size: Int, numRead: Int, numWrite: Int, numForward: Int) extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
+  val io = IO(new Bundle() {
+    val raddr = Vec(numRead,  Input(UInt(log2Up(size).W)))
+    val rdata = Vec(numRead,  Output(new SQDataEntry))
+    val wen   = Vec(numWrite, Input(Bool()))
+    val waddr = Vec(numWrite, Input(UInt(log2Up(size).W)))
+    val wdata = Vec(numWrite, Input(new SQDataEntry))
+
+    val needForward = Input(Vec(numForward, Vec(2, UInt(size.W))))
+    val forwardMask = Vec(numForward, Output(Vec(8, Bool())))
+    val forwardData = Vec(numForward, Output(Vec(8, UInt(8.W))))
+  })
+
+  val data8 = Seq.fill(8)(Module(new SQData8Module(size, numRead, numWrite, numForward)))
 
-  io.debug := data
+  // writeback to lq/sq
+  for (i <- 0 until numWrite) {
+    // write to data8
+    for (j <- 0 until 8) {
+      data8(j).io.waddr(i) := io.waddr(i)
+      data8(j).io.wdata(i).valid := io.wdata(i).mask(j)
+      data8(j).io.wdata(i).data := io.wdata(i).data(8*(j+1)-1, 8*j)
+      data8(j).io.wen(i) := io.wen(i)
+    }
+  }
+
+  // destorequeue read data
+  for (i <- 0 until numRead) {
+    for (j <- 0 until 8) {
+      data8(j).io.raddr(i) := io.raddr(i)
+    }
+    io.rdata(i).mask := VecInit((0 until 8).map(j => data8(j).io.rdata(i).valid)).asUInt
+    io.rdata(i).data := VecInit((0 until 8).map(j => data8(j).io.rdata(i).data)).asUInt
+  }
+
+  // DataModuleTemplate should not be used when there're any write conflicts
+  for (i <- 0 until numWrite) {
+    for (j <- i+1 until numWrite) {
+      assert(!(io.wen(i) && io.wen(j) && io.waddr(i) === io.waddr(j)))
+    }
+  }
+
+  (0 until numForward).map(i => {
+    // parallel fwd logic
+    for (j <- 0 until 8) {
+      data8(j).io.needForward(i) <> io.needForward(i)
+      io.forwardMask(i) := VecInit((0 until 8).map(j => data8(j).io.forwardValid(i)))
+      io.forwardData(i) := VecInit((0 until 8).map(j => data8(j).io.forwardData(i)))
+    }
+  })
 }
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