Backend: convert floating point data between ieee and recode fmt in fp block

src/main/scala/xiangshan/XSCore.scala

@@ -339,10 +339,8 @@ class XSCore()(implicit p: config.Parameters) extends LazyModule
   val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
   val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
 
-  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
-  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
-  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
-  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
+  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(_.writeFpRf)
+  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(_.writeIntRf)
 
   // outer facing nodes
   val frontend = LazyModule(new Frontend())
@@ -350,12 +348,10 @@ class XSCore()(implicit p: config.Parameters) extends LazyModule
   val ptw = LazyModule(new PTW())
   val l2Prefetcher = LazyModule(new L2Prefetcher())
   val memBlock = LazyModule(new MemBlock(
-    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
+    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp,
     slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
-    fastFpOut = Seq(),
-    slowFpOut = loadExuConfigs,
-    fastIntOut = Seq(),
-    slowIntOut = loadExuConfigs
+    fastWakeUpOut = Seq(),
+    slowWakeUpOut = loadExuConfigs
   ))
 
   lazy val module = new XSCoreImp(this)
@@ -385,14 +381,12 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
   val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
 
-  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
-  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
-  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
-  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
+  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(_.writeFpRf)
+  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(_.writeIntRf)
 
   val ctrlBlock = Module(new CtrlBlock)
   val integerBlock = Module(new IntegerBlock(
-    fastWakeUpIn = fpBlockFastWakeUpInt,
+    fastWakeUpIn = Seq(),
     slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs,
     fastFpOut = intBlockFastWakeUpFp,
     slowFpOut = intBlockSlowWakeUpFp,
@@ -402,9 +396,9 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   val floatBlock = Module(new FloatBlock(
     fastWakeUpIn = intBlockFastWakeUpFp,
     slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs,
-    fastFpOut = fpBlockFastWakeUpFp,
+    fastFpOut = Seq(),
     slowFpOut = fpBlockSlowWakeUpFp,
-    fastIntOut = fpBlockFastWakeUpInt,
+    fastIntOut = Seq(),
     slowIntOut = fpBlockSlowWakeUpInt
   ))
 
@@ -430,14 +424,24 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock
   ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock
 
+  val memBlockWakeUpInt = memBlock.io.wakeUpOut.slow.map(raw => {
+    val n = WireInit(raw)
+    n.valid := raw.valid && raw.bits.uop.ctrl.rfWen
+    n
+  })
+  val memBlockWakeUpFp = memBlock.io.wakeUpOut.slow.map(raw => {
+    val n = WireInit(raw)
+    n.valid := raw.valid && raw.bits.uop.ctrl.fpWen
+    n
+  })
   integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops
   integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast
-  integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow
+  integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlockWakeUpInt
   integerBlock.io.toMemBlock <> memBlock.io.fromIntBlock
 
   floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops
   floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast
-  floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow
+  floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlockWakeUpFp
   floatBlock.io.toMemBlock <> memBlock.io.fromFpBlock
 
 

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -6,7 +6,8 @@ import xiangshan._
 import utils._
 import xiangshan.backend.regfile.Regfile
 import xiangshan.backend.exu._
-import xiangshan.backend.issue.{ReservationStation}
+import xiangshan.backend.issue.ReservationStation
+import xiangshan.mem.HasLoadHelper
 
 
 class FpBlockToCtrlIO extends XSBundle {
@@ -22,7 +23,7 @@ class FloatBlock
   slowFpOut: Seq[ExuConfig],
   fastIntOut: Seq[ExuConfig],
   slowIntOut: Seq[ExuConfig]
-) extends XSModule with HasExeBlockHelper {
+) extends XSModule with HasExeBlockHelper with HasLoadHelper {
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToFpBlockIO)
     val toCtrlBlock = new FpBlockToCtrlIO
@@ -39,6 +40,19 @@ class FloatBlock
   val redirect = io.fromCtrlBlock.redirect
   val flush = io.fromCtrlBlock.flush
 
+  require(fastWakeUpIn.isEmpty)
+  val wakeUpInReg = Wire(Flipped(new WakeUpBundle(fastWakeUpIn.size, slowWakeUpIn.size)))
+  for((in, inReg) <- io.wakeUpIn.slow.zip(wakeUpInReg.slow)){
+    inReg.ready := true.B
+    PipelineConnect(in, inReg, inReg.fire(), in.bits.uop.roqIdx.needFlush(redirect, flush))
+  }
+  val wakeUpInRecode = WireInit(wakeUpInReg)
+  for(i <- wakeUpInReg.slow.indices){
+    if(i != 0){
+      wakeUpInRecode.slow(i).bits.data := fpRdataHelper(wakeUpInReg.slow(i).bits.uop, wakeUpInReg.slow(i).bits.data)
+    }
+  }
+
   val fpRf = Module(new Regfile(
     numReadPorts = NRFpReadPorts,
     numWirtePorts = NRFpWritePorts,
@@ -71,11 +85,10 @@ class FloatBlock
     val readFpRf = cfg.readFpRf
 
     val inBlockWbData = exeUnits.filter(e => e.config.hasCertainLatency && readFpRf).map(_.io.toFp.bits.data)
-    val writeBackData = inBlockWbData ++ io.wakeUpIn.fast.map(_.bits.data)
-    val fastPortsCnt = writeBackData.length
+    val fastPortsCnt = inBlockWbData.length
 
     val inBlockListenPorts = exeUnits.filter(e => e.config.hasUncertainlatency && readFpRf).map(_.io.toFp)
-    val slowPorts = inBlockListenPorts ++ io.wakeUpIn.slow
+    val slowPorts = inBlockListenPorts ++ wakeUpInRecode.slow
     val slowPortsCnt = slowPorts.length
 
     println(s"${i}: exu:${cfg.name} fastPortsCnt: ${fastPortsCnt} " +
@@ -99,7 +112,7 @@ class FloatBlock
     rs.io.srcRegValue(1) := src2Value(readPortIndex(i))
     if (cfg.fpSrcCnt > 2) rs.io.srcRegValue(2) := src3Value(readPortIndex(i))
 
-    rs.io.fastDatas <> writeBackData
+    rs.io.fastDatas <> inBlockWbData
     for ((x, y) <- rs.io.slowPorts.zip(slowPorts)) {
       x.valid := y.fire()
       x.bits := y.bits
@@ -123,32 +136,21 @@ class FloatBlock
       raw.valid := x.io.fastUopOut.valid && raw.bits.ctrl.fpWen
       raw
     })
-    rs.io.fastUopsIn <> inBlockUops ++  io.wakeUpIn.fastUops
+    rs.io.fastUopsIn <> inBlockUops
   }
 
-  io.wakeUpFpOut.fastUops <> reservedStations.filter(
-    rs => fpFastFilter(rs.exuCfg)
-  ).map(_.io.fastUopOut).map(fpValid)
-
-  io.wakeUpFpOut.fast <> exeUnits.filter(
-    x => fpFastFilter(x.config)
-  ).map(_.io.toFp)
-
-  io.wakeUpFpOut.slow <> exeUnits.filter(
-    x => fpSlowFilter(x.config)
-  ).map(_.io.toFp)
-
-  io.wakeUpIntOut.fastUops <> reservedStations.filter(
-    rs => intFastFilter(rs.exuCfg)
-  ).map(_.io.fastUopOut).map(intValid)
+  def connectAndConvertToIEEE(in: DecoupledIO[ExuOutput]) = {
+    val outReg = Wire(DecoupledIO(new ExuOutput))
+    outReg.ready := true.B
+    PipelineConnect(in, outReg, outReg.fire(), in.bits.uop.roqIdx.needFlush(redirect, flush))
+    val outIeee = WireInit(outReg)
+    outIeee.bits.data := ieee(outReg.bits.data)
+    outIeee
+  }
 
-  io.wakeUpIntOut.fast <> exeUnits.filter(
-    x => intFastFilter(x.config)
-  ).map(_.io.toInt)
+  io.wakeUpFpOut.slow <> exeUnits.filter(_.config.writeFpRf).map(_.io.toFp).map(connectAndConvertToIEEE)
 
-  io.wakeUpIntOut.slow <> exeUnits.filter(
-    x => intSlowFilter(x.config)
-  ).map(_.io.toInt)
+  io.wakeUpIntOut.slow <> exeUnits.filter(_.config.writeIntRf).map(_.io.toInt)
 
 
   // read fp rf from ctrl block
@@ -160,7 +162,7 @@ class FloatBlock
     NRFpWritePorts,
     isFp = true
   ))
-  fpWbArbiter.io.in <> exeUnits.map(_.io.toFp) ++ io.wakeUpIn.fast ++ io.wakeUpIn.slow
+  fpWbArbiter.io.in <> exeUnits.map(_.io.toFp) ++ wakeUpInRecode.slow
 
   // set busytable and update roq
   io.toCtrlBlock.wbRegs <> fpWbArbiter.io.out

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -30,29 +30,19 @@ class FpBlockToMemBlockIO extends XSBundle {
 }
 
 class MemBlock(
-  fastWakeUpIn: Seq[ExuConfig],
-  slowWakeUpIn: Seq[ExuConfig],
-  fastFpOut: Seq[ExuConfig],
-  slowFpOut: Seq[ExuConfig],
-  fastIntOut: Seq[ExuConfig],
-  slowIntOut: Seq[ExuConfig]
+  val fastWakeUpIn: Seq[ExuConfig],
+  val slowWakeUpIn: Seq[ExuConfig],
+  val fastWakeUpOut: Seq[ExuConfig],
+  val slowWakeUpOut: Seq[ExuConfig]
 )(implicit p: Parameters) extends LazyModule {
 
   val dcache = LazyModule(new DCache())
   val uncache = LazyModule(new Uncache())
 
-  lazy val module = new MemBlockImp(fastWakeUpIn, slowWakeUpIn, fastFpOut, slowFpOut, fastIntOut, slowIntOut)(this)
+  lazy val module = new MemBlockImp(this)
 }
 
-class MemBlockImp
-(
-  fastWakeUpIn: Seq[ExuConfig],
-  slowWakeUpIn: Seq[ExuConfig],
-  fastFpOut: Seq[ExuConfig],
-  slowFpOut: Seq[ExuConfig],
-  fastIntOut: Seq[ExuConfig],
-  slowIntOut: Seq[ExuConfig]
-) (outer: MemBlock) extends LazyModuleImp(outer)
+class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   with HasXSParameter
   with HasExceptionNO
   with HasXSLog
@@ -60,6 +50,11 @@ class MemBlockImp
   with HasExeBlockHelper
 {
 
+  val fastWakeUpIn = outer.fastWakeUpIn
+  val slowWakeUpIn = outer.slowWakeUpIn
+  val fastWakeUpOut = outer.fastWakeUpOut
+  val slowWakeUpOut = outer.slowWakeUpOut
+
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToLsBlockIO)
     val fromIntBlock = Flipped(new IntBlockToMemBlockIO)
@@ -67,8 +62,7 @@ class MemBlockImp
     val toCtrlBlock = new LsBlockToCtrlIO
 
     val wakeUpIn = new WakeUpBundle(fastWakeUpIn.size, slowWakeUpIn.size)
-    val wakeUpFpOut = Flipped(new WakeUpBundle(fastFpOut.size, slowFpOut.size))
-    val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOut.size, slowIntOut.size))
+    val wakeUpOut = Flipped(new WakeUpBundle(fastWakeUpOut.size, slowWakeUpOut.size))
 
     val ptw = new TlbPtwIO
     val sfence = Input(new SfenceBundle)
@@ -197,8 +191,8 @@ class MemBlockImp
   io.wakeUpIn.fast.foreach(_.ready := true.B)
   io.wakeUpIn.slow.foreach(_.ready := true.B)
 
-  io.wakeUpFpOut.slow  <> fpExeWbReqs
-  io.wakeUpIntOut.slow <> intExeWbReqs
+  // TODO: connect this
+  io.wakeUpOut.slow <> DontCare
 
   // load always ready
   fpExeWbReqs.foreach(_.ready := true.B)