rob, mmu: fix bug of not specifying signal width

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -997,7 +997,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   }
 
   //difftest signals
-  val firstValidCommit = (deqPtr + PriorityMux(io.commits.commitValid, VecInit(List.tabulate(CommitWidth)(_.U)))).value
+  val firstValidCommit = (deqPtr + PriorityMux(io.commits.commitValid, VecInit(List.tabulate(CommitWidth)(_.U(log2Up(CommitWidth).W))))).value
 
   val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
   val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))

src/main/scala/xiangshan/cache/mmu/MMUConst.scala

@@ -117,7 +117,7 @@ trait HasTlbConst extends HasXSParameter {
 
   def replaceWrapper(v: UInt, lruIdx: UInt): UInt = {
     val width = v.getWidth
-    val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U)))
+    val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W))))
     val full = Cat(v).andR
     Mux(full, lruIdx, emptyIdx)
   }

src/main/scala/xiangshan/cache/mmu/PageTableCache.scala

@@ -280,7 +280,7 @@ class PtwCache(parentName:String = "Unknown")(implicit p: Parameters) extends XS
     val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas)
     val hitWayData = hitWayEntry.entries
     val hit = ParallelOR(hitVec)
-    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U))
+    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U(log2Up(l2tlbParams.l2nWays).W)))
     val eccError = hitWayEntry.decode()
 
     ridx.suggestName(s"l2_ridx")
@@ -326,7 +326,7 @@ class PtwCache(parentName:String = "Unknown")(implicit p: Parameters) extends XS
     val hitWayData = hitWayEntry.entries
     val hitWayEcc = hitWayEntry.ecc
     val hit = ParallelOR(hitVec)
-    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U))
+    val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U(log2Up(l2tlbParams.l3nWays).W)))
     val eccError = hitWayEntry.decode()
 
     when (hit && stageCheck_valid_1cycle) { ptwl3replace.access(genPtwL3SetIdx(check_vpn), hitWay) }

src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala

@@ -281,7 +281,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
     mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i)
   }
 
-  val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U))
+  val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W)))
 
   // duplicate req
   // to_wait: wait for the last to access mem, set to mem_resp