lsq,dpq,roq: fix validCounter width

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -34,7 +34,7 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int) extends XSModule with H
   val tailPtr = RegInit(VecInit((0 until enqnum).map(_.U.asTypeOf(new CircularQueuePtr(size)))))
   val tailPtrMask = UIntToMask(tailPtr(0).value, size)
   // valid entries counter
-  val validCounter = RegInit(0.U(log2Ceil(size).W))
+  val validCounter = RegInit(0.U(log2Ceil(size + 1).W))
   val allowEnqueue = RegInit(true.B)
 
   val isTrueEmpty = ~Cat((0 until size).map(i => stateEntries(i) === s_valid)).orR

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -115,7 +115,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   val enqPtr = RegInit(0.U.asTypeOf(new RoqPtr))
   val deqPtrVec = RegInit(VecInit((0 until CommitWidth).map(_.U.asTypeOf(new RoqPtr))))
   val walkPtrVec = Reg(Vec(CommitWidth, new RoqPtr))
-  val validCounter = RegInit(0.U(log2Ceil(RoqSize).W))
+  val validCounter = RegInit(0.U(log2Ceil(RoqSize + 1).W))
   val allowEnqueue = RegInit(true.B)
 
   val enqPtrVec = VecInit((0 until RenameWidth).map(i => enqPtr + PopCount(io.enq.needAlloc.take(i))))

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -62,7 +62,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
 
   val enqPtrExt = RegInit(VecInit((0 until RenameWidth).map(_.U.asTypeOf(new LqPtr))))
   val deqPtrExt = RegInit(0.U.asTypeOf(new LqPtr))
-  val validCounter = RegInit(0.U(log2Ceil(LoadQueueSize).W))
+  val validCounter = RegInit(0.U(log2Ceil(LoadQueueSize + 1).W))
   val allowEnqueue = RegInit(true.B)
 
   val enqPtr = enqPtrExt(0).value

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -58,7 +58,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
   require(StoreQueueSize > RenameWidth)
   val enqPtrExt = RegInit(VecInit((0 until RenameWidth).map(_.U.asTypeOf(new SqPtr))))
   val deqPtrExt = RegInit(VecInit((0 until StorePipelineWidth).map(_.U.asTypeOf(new SqPtr))))
-  val validCounter = RegInit(0.U(log2Ceil(LoadQueueSize).W))
+  val validCounter = RegInit(0.U(log2Ceil(LoadQueueSize + 1).W))
   val allowEnqueue = RegInit(true.B)
 
   val enqPtr = enqPtrExt(0).value