csr: add smblockctl for customized control of memory block (#634)

src/main/scala/xiangshan/Bundle.scala

@@ -532,11 +532,14 @@ class CustomCSRCtrlIO extends XSBundle {
   // Prefetcher
   val l1plus_pf_enable = Output(Bool())
   val l2_pf_enable = Output(Bool())
+  // Labeled XiangShan
   val dsid = Output(UInt(8.W)) // TODO: DsidWidth as parameter
-  // Load violation predict
+  // Load violation predictor
   val lvpred_disable = Output(Bool())
   val no_spec_load = Output(Bool())
   val waittable_timeout = Output(UInt(5.W))
-  // Branch predicter
+  // Branch predictor
   val bp_ctrl = Output(new BPUCtrl)
-}
\ No newline at end of file
+  // Memory Block
+  val sbuffer_threshold = Output(UInt(4.W))
+}

src/main/scala/xiangshan/XSCore.scala

@@ -465,6 +465,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   integerBlock.io.fenceio.sfence <> memBlock.io.sfence
   integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer
 
+  memBlock.io.csrCtrl <> integerBlock.io.csrio.customCtrl
   memBlock.io.tlbCsr <> RegNext(integerBlock.io.csrio.tlb)
   memBlock.io.lsqio.roq <> ctrlBlock.io.roqio.lsq
   memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.uop.lqIdx

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -78,6 +78,8 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
       val exceptionAddr = new ExceptionAddrIO // to csr
       val roq = Flipped(new RoqLsqIO) // roq to lsq
     }
+
+    val csrCtrl = Flipped(new CustomCSRCtrlIO)
   })
   val difftestIO = IO(new Bundle() {
     val fromSbuffer = new Bundle() {
@@ -304,6 +306,7 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
   lsq.io.sqempty        <> sbuffer.io.sqempty
 
   // Sbuffer
+  sbuffer.io.csrCtrl    <> RegNext(io.csrCtrl)
   sbuffer.io.dcache     <> dcache.io.lsu.store
   sbuffer.io.dcache.resp.valid := RegNext(dcache.io.lsu.store.resp.valid)
   sbuffer.io.dcache.resp.bits := RegNext(dcache.io.lsu.store.resp.bits)

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -355,6 +355,11 @@ class CSR extends FunctionUnit with HasCSRConst
   csrio.customCtrl.no_spec_load := slvpredctl(1)
   csrio.customCtrl.waittable_timeout := slvpredctl(8, 4)
 
+  // smblockctl: memory block configurations
+  // bits 0-3: store buffer flush threshold (default: 8 entries)
+  val smblockctl = RegInit(UInt(XLEN.W), "h7".U)
+  csrio.customCtrl.sbuffer_threshold := smblockctl(3, 0)
+
   val tlbBundle = Wire(new TlbCsrBundle)
   tlbBundle.satp := satp.asTypeOf(new SatpStruct)
   csrio.tlb := tlbBundle
@@ -486,6 +491,7 @@ class CSR extends FunctionUnit with HasCSRConst
     MaskedRegMap(Spfctl, spfctl),
     MaskedRegMap(Sdsid, sdsid),
     MaskedRegMap(Slvpredctl, slvpredctl),
+    MaskedRegMap(Smblockctl, smblockctl),
 
     //--- Machine Information Registers ---
     MaskedRegMap(Mvendorid, mvendorid, 0.U, MaskedRegMap.Unwritable),

src/main/scala/xiangshan/backend/fu/util/CSRConst.scala

@@ -53,8 +53,8 @@ trait HasCSRConst {
   // Supervisor Custom Read/Write
   val Sbpctl        = 0x5C0
   val Spfctl        = 0x5C1
-
   val Slvpredctl    = 0x5C2
+  val Smblockctl    = 0x5C3
 
   val Sdsid         = 0x9C0
 

src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala

@@ -56,6 +56,7 @@ class NewSbuffer extends XSModule with HasSbufferConst {
     val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
     val sqempty = Input(Bool())
     val flush = Flipped(new SbufferFlushBundle)
+    val csrCtrl = Flipped(new CustomCSRCtrlIO)
   })
   val difftestIO = IO(new Bundle() {
     val sbufferResp = Output(Bool())
@@ -257,7 +258,7 @@ class NewSbuffer extends XSModule with HasSbufferConst {
   val do_eviction = Wire(Bool())
   val empty = Cat(stateVec.map(s => isInvalid(s))).andR() && !Cat(io.in.map(_.valid)).orR()
 
-  do_eviction := validCount >= 12.U
+  do_eviction := validCount >= RegNext(io.csrCtrl.sbuffer_threshold +& 1.U)
 
   io.flush.empty := RegNext(empty && io.sqempty)
   // lru.io.flush := sbuffer_state === x_drain_sbuffer && empty