Sim dev

See merge request projectn/noop!19

This reverts commit e2e2e3f1.

* For VGA, the original wmask seems correct. But now UART does not work.

* only support write

* Should assert req.ready once it is accepted by the slave. The master
  should guarantee only one request is in-flight.

device,AXI4VGA: fix vga bug, but still not perfect

See merge request projectn/noop!18

* Due to the modification of AXI4Slave, now AXI4RAM has 2 cycle of
  latency.
* The display is still not perfect. Some vertical lines are still wrong.
* We should modify the vga code to be independent of the behavior of
  AXI4RAM.

fpga,board,zedboard: support rv64

See merge request projectn/noop!17

Add axu3cg

See merge request projectn/noop!16

* The official version from github seems not work. Maybe there is some
  difference between zcu102 and axu3cg.

test,uart: preset some keys and them generate random keys

See merge request projectn/noop!15

* now we can control the characters in PAL to trigger a battle

Coh

See merge request projectn/noop!14

* BTB should also be flushed when executing fence.i
* Now we can let the init program load PAL to run.

* Flushing ICache will cost cycles equal to the number of cache sets,
  which is 512 now. Before finishing the flush, instruction fetch will
  be stalled.
* Now we really pass nexum-am/tests/cachetest/test/loader.c.

* When executing fence.i, the pipeline and ICache will be flushed. New
  instructions will be fetched from memory, or DCache with coherence
  support.
* With fence.i, we should pass nexus-am/tests/cachetest/test/loader.c.

This reverts commit 7c95c717.

* The original bug is caused by 32-bit width of CacheProbeStage, which
  is merged after rv64 and forget to change the width to 64-bit.

Rv64 fpga

See merge request projectn/noop!13

* AXI requires araddr to be aligned with arsize

* 64-bit multiplier consumes more DSPs on FPGA than 32-bit multiplier.
  Cascaded DSPs lead to poor timing, and must improve by more registers.