In this commit, we add License for XiangShan project. 

* Update mill and rocket-chip

* [WIP] auto generate dts by diplomacy

MinimalConfig limited queues' size, disabled TAGE to limit generated
verilog size

Usage: change `config = DefaultConfig` to `config = MinimalConfig`
in Top.scala / SimTop.scala

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* Fixed perf counter does not print bug in BlockInclusiveCache.

* BlockInclusiveCache: Dont Probe L1 On Hint Hit.

* L2 use UncachedGet, L3 cache Get.

* Bump L2
Co-authored-by: NLinJiawei <linjiav@outlook.com>

* Add ResetRegGen module to generate reset signals for different modules

To meet physical design requirements, reset signals for different modules
need to be generated respectively. This commit adds a ResetRegGen module
to automatically generate reset registers and connects different reset
signals to different modules, including l3cache, l2cache, core.
L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are
reset one by one.

L2 and L3 Only enablePerf when XSCore enables perf.

* l2,timing: bump l2/l3 cache

This will necessarily add several cycles to L2/L3 cache responsing time.

* l2,l3: bump timing tweaks

Resolved timeout in debian boot.
Remove repeat feature to avoid directory disturbing
(repeat allows to use previous tag and victim info which is dangerous).

TODO:
- [ ] Another directory atomicity weakness that heavy l1 release can
      overwrite l3tol2 probe directory update, for example:
      l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback
               l2.probeAck.BtoB write non-dirty (not saved)
      l3 think l2 is branch, but l2 is still trunk.
      But forbid nestB and nestC can cause deadlock...
- [ ] Delay bankedStore one more cycle for L3 large sram timing.

* l2,l3: change mshr amount to 15

* Top: remove extra axi ID bits

* Re-add AXI4UserYanker
Co-authored-by: NLinJiawei <linjiav@outlook.com>

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog
Co-authored-by: NLinJiawei <linjiav@outlook.com>