arch,riscv: fix supervisor timer interrupt

am/src/nemu/isa/riscv/mtime.S

@@ -28,8 +28,9 @@ is_timer:
         add a3, a3, a2
         sd a3, 0(a1)
 
-        # raise a supervisor software interrupt.
-        csrwi sip, 2
+        # raise a supervisor timer interrupt.
+	li a3, 32
+        csrw mip, a3
         j end_of_intr
 
 is_ext:

am/src/xs/isa/riscv/clint.c

@@ -48,7 +48,7 @@ void init_timer() {
  */
 void enable_timer() {
   // set machine timer interrupt
-  asm volatile("csrs mie, %0" : : "r"((1 << 7) | (1 << 1)));
+  asm volatile("csrs mie, %0" : : "r"((1 << 7) | (1 << 5) | (1 << 1)));
 }
 
 /*
@@ -56,5 +56,5 @@ void enable_timer() {
  */
 void disable_timer() {
   // unset machine timer interrupt
-  asm volatile("csrc mie, %0" : : "r"((1 << 7) | (1 << 1)));
-}
\ No newline at end of file
+  asm volatile("csrc mie, %0" : : "r"((1 << 7) | (1 << 5) | (1 << 1)));
+}