arch,riscv: fix supervisor timer interrupt

Add drivers and tests for southlake

Add extra RISC-V PMP tests

* used to test nanhu's alias mechanism

Add LINUX_GNU_TOOLCHAIN=1 in make command to use riscv64-linux-gnu-
toolchain

* define `TEST_L3` in beu.c to test l3 cache ecc error
* undefine `TEST_L3` in beu.c to test beu

* Test the workflow of bus error unit when an ecc error occurs

amtest,xsconfig: Support 256 external interrupt bits tests

* Now the following four testcases can be covered:
* Dma_master send write to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send write to cpu_dma, and miss the l3, so there will i_soc.mem port write real ddr
* Dma_master send read to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send read to cpu_dma, and miss the l3, so there will i_soc.mem port read read ddr

Merge branch 'southlake' into master

shrink PMEM size to reduce test setup time
add sfence.vma before accessing any newly mapped virtual addresses