de1_riscv_v5.v

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

`define USECLOCK50

module de1_riscv_v5(

	//////////// ADC //////////
	output		          		ADC_CONVST,
	output		          		ADC_DIN,
	input 		          		ADC_DOUT,
	output		          		ADC_SCLK,

	//////////// Audio //////////
	input 		          		AUD_ADCDAT,
	inout 		          		AUD_ADCLRCK,
	inout 		          		AUD_BCLK,
	output		          		AUD_DACDAT,
	inout 		          		AUD_DACLRCK,
	output		          		AUD_XCK,

	//////////// CLOCK //////////
	input 		          		CLOCK2_50,
	input 		          		CLOCK3_50,
	input 		          		CLOCK4_50,
	input 		          		CLOCK_50,

	//////////// SDRAM //////////
	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N,

	//////////// I2C for Audio and Video-In //////////
	output		          		FPGA_I2C_SCLK,
	inout 		          		FPGA_I2C_SDAT,

	//////////// SEG7 //////////
	output		     [6:0]		HEX0,
	output		     [6:0]		HEX1,
	output		     [6:0]		HEX2,
	output		     [6:0]		HEX3,
	output		     [6:0]		HEX4,
	output		     [6:0]		HEX5,

	//////////// IR //////////
	input 		          		IRDA_RXD,
	output		          		IRDA_TXD,

	//////////// KEY //////////
	input 		     [3:0]		KEY,

	//////////// LED //////////
	output		     [9:0]		LEDR,

	//////////// PS2 //////////
	inout 		          		PS2_CLK,
	inout 		          		PS2_CLK2,
	inout 		          		PS2_DAT,
	inout 		          		PS2_DAT2,

	//////////// SW //////////
	input 		     [9:0]		SW,

	//////////// Video-In //////////
	input 		          		TD_CLK27,
	input 		     [7:0]		TD_DATA,
	input 		          		TD_HS,
	output		          		TD_RESET_N,
	input 		          		TD_VS,

	//////////// VGA //////////
	output		          		VGA_BLANK_N,
	output		     [7:0]		VGA_B,
	output		          		VGA_CLK,
	output		     [7:0]		VGA_G,
	output		          		VGA_HS,
	output		     [7:0]		VGA_R,
	output		          		VGA_SYNC_N,
	output		          		VGA_VS,

	//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
	inout 		    [35:0]		GPIO
);


  wire        uart_tx;
  wire        uart_rx;
  assign GPIO[5] = uart_tx;
  assign GPIO[7] = 1'bz;
  assign      uart_rx = GPIO[7];

  assign LEDR[0] = uart_tx;
  assign LEDR[1] = uart_rx;

`ifdef USECLOCK50
	wire wClk = CLOCK_50;
`else
	wire clk100MHz, clk75MHz, clklocked;
	clk100M clk100(.refclk(CLOCK_50),
	               .rst(~KEY[3]),
				   .outclk_0(clk100MHz), 
				   .outclk_1(clk75MHz),
				   .locked(clklocked));
				   
	wire wClk = clk100MHz;
`endif
	wire nwReset = KEY[3];

    wire wWrite, wRead;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
    wire [3:0]  bWriteMask;

`define TESTALEXUART_

`ifdef TESTALEXUART
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;

wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;

uart
uart_inst (
    .clk(wClk),
    .rst(~nwReset),
    // AXI input
    .s_axis_tdata(uart_tx_axis_tdata),
    .s_axis_tvalid(uart_tx_axis_tvalid),
    .s_axis_tready(uart_tx_axis_tready),
    // AXI output
    .m_axis_tdata(uart_rx_axis_tdata),
    .m_axis_tvalid(uart_rx_axis_tvalid),
    .m_axis_tready(uart_rx_axis_tready),
    // uart
    .rxd(uart_rx),
    .txd(uart_tx),
    // status
    .tx_busy(),
    .rx_busy(),
    .rx_overrun_error(),
    .rx_frame_error(),
    // configuration
    .prescale(50000000/(115200*8))
);

always @(posedge wClk or negedge nwReset) begin
    if (~nwReset) begin
        uart_tx_axis_tdata <= 0;
        uart_tx_axis_tvalid <= 0;
        uart_rx_axis_tready <= 0;
    end else begin
        if (uart_tx_axis_tvalid) begin
            // attempting to transmit a byte
            // so can't receive one at the moment
            uart_rx_axis_tready <= 0;
            // if it has been received, then clear the valid flag
            if (uart_tx_axis_tready) begin
                uart_tx_axis_tvalid <= 0;
            end
        end else begin
            // ready to receive byte
            uart_rx_axis_tready <= 1;
            if (uart_rx_axis_tvalid) begin
                // got one, so make sure it gets the correct ready signal
                // (either clear it if it was set or set it if we just got a
                // byte out of waiting for the transmitter to send one)
                uart_rx_axis_tready <= ~uart_rx_axis_tready;
                // send byte back out
                uart_tx_axis_tdata <= uart_rx_axis_tdata;
                uart_tx_axis_tvalid <= 1;
            end
        end
    end
end

`else
	uart_ctrl uart_ctrl(
		.wClk(wClk), 
		.nwReset(nwReset),
		.wRead(((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0), 
		.bReadAddr(bReadAddr),
		.wWrite(((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0), 
		.bWriteAddr(bWriteAddr),
		.bWriteData(bWriteData),
		.bReadData(bReadDataUart),
		.uart_tx(uart_tx), 
		.uart_rx(uart_rx),
		.dataready(LEDR[2]),
		.sendready(LEDR[3]),
		.sendfull(LEDR[4]),
		.recvempty(LEDR[5])
	);
`endif

		/* AXI signal */
		// Write Address
		wire			wAWValid;
		wire [31 : 0]	bAWAddr;
		wire [2 : 0]	bAWProt;
		wire			wAWReady = 1'b1;

		// Write Data 
		wire			wWValid;
		wire [31 : 0]	bWData;
		wire [3 : 0]	bWStrb;
		wire			wWReady = 1'b1;

		// Write Response
		wire			wBReady;
		wire [1 : 0]	bBResp;
		wire			wBValid = 1'b1;

		assign wWrite = wAWValid;
		assign bWriteAddr = bAWAddr;
		assign bWriteData = bWData;
		assign bWriteMask = ~bWStrb; 

		reg            read_r;
		always@(posedge wClk)
			read_r <= wRead;
		// ReadAddr
		wire			wARValid;
		wire [31 : 0]	bARAddr;
		wire [2 : 0]	bARProt;
		wire			wARReady = 1'b1;

		assign bReadAddr = bARAddr;
		assign wRead = wARValid;

		//ReadData
		wire			wRReady;
		wire			wRValid = read_r;
		wire [31 : 0]	bRData = bReadDataUart;
		wire [1 : 0]	bRResp = 1'b0;

		riscv_core_with_axi_master riscv_core_with_axi(
			// clock and reset
			wClk,
			nwReset,
	
			// Write Address
			wAWValid,
			bAWAddr,
			bAWProt,
			wAWReady,
	
			// Write Data 
			wWValid,
			bWData,
			bWStrb,
			wWReady,
	
			// Write Response
			wBReady,
			bBResp,
			wBValid,
	
			// ReadAddr
			wARValid,
			bARAddr,
			bARProt,
			wARReady,
	
			//ReadData
			wRReady,
			wRValid,
			bRData,
			bRResp
		);

	reg [6:0] led0;
	reg [6:0] led1;
	reg [6:0] led2;
	reg [6:0] led3;
	reg [6:0] led4;
	reg [6:0] led5;
	assign HEX0 = ~led0;
	assign HEX1 = ~led1;
	assign HEX2 = ~led2;
	assign HEX3 = ~led3;
	assign HEX4 = ~led4;
	assign HEX5 = ~led5;

	

	always @(posedge wClk) begin
		if (!nwReset) begin
			led0 <= 7'h3f;
			led1 <= 7'h3f;
			led2 <= 7'h3f;
			led3 <= 7'h3f;
			led4 <= 7'h3f;
			led5 <= 7'h3f;
		end else begin
			if (SW[8]) begin
				led0 <= 7'h06;
				led1 <= 7'h06;
				led2 <= 7'h06;
				led3 <= 7'h07;
				led4 <= 7'h07;
				led5 <= 7'h07;				
			end
			else if (SW[9]) begin
				led0 <= 7'h3f;
				led1 <= 7'h06;
				led2 <= 7'h5b;
				led3 <= 7'h4f;
				led4 <= 7'h66;
				led5 <= 7'h6d;				
			end
			else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
				if (bWriteAddr[7:0] == 8'h10) begin
					led0 <= bWriteData[6:0];
					led1 <= bWriteData[14:8];
					led2 <= bWriteData[22:16];
					led3 <= bWriteData[30:24];
				end else if (bWriteAddr[7:0] == 8'h14) begin
					led4 <= bWriteData[6:0];
					led5 <= bWriteData[14:8];
				end
			end
		end
	end


endmodule