risc_axi_v5_top.v

//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date        : Mon Sep 13 21:25:05 2021
//Host        : DESKTOP-I91JIJO running 64-bit major release  (build 9200)
//Command     : generate_target risc_axi_v5_top.bd
//Design      : risc_axi_v5_top
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module m00_couplers_imp_DIBHKD
   (M_ACLK,
    M_ARESETN,
    M_AXI_araddr,
    M_AXI_arprot,
    M_AXI_arready,
    M_AXI_arvalid,
    M_AXI_awaddr,
    M_AXI_awprot,
    M_AXI_awready,
    M_AXI_awvalid,
    M_AXI_bready,
    M_AXI_bresp,
    M_AXI_bvalid,
    M_AXI_rdata,
    M_AXI_rready,
    M_AXI_rresp,
    M_AXI_rvalid,
    M_AXI_wdata,
    M_AXI_wready,
    M_AXI_wstrb,
    M_AXI_wvalid,
    S_ACLK,
    S_ARESETN,
    S_AXI_araddr,
    S_AXI_arprot,
    S_AXI_arready,
    S_AXI_arvalid,
    S_AXI_awaddr,
    S_AXI_awprot,
    S_AXI_awready,
    S_AXI_awvalid,
    S_AXI_bready,
    S_AXI_bresp,
    S_AXI_bvalid,
    S_AXI_rdata,
    S_AXI_rready,
    S_AXI_rresp,
    S_AXI_rvalid,
    S_AXI_wdata,
    S_AXI_wready,
    S_AXI_wstrb,
    S_AXI_wvalid);
  input M_ACLK;
  input M_ARESETN;
  output [31:0]M_AXI_araddr;
  output [2:0]M_AXI_arprot;
  input M_AXI_arready;
  output M_AXI_arvalid;
  output [31:0]M_AXI_awaddr;
  output [2:0]M_AXI_awprot;
  input M_AXI_awready;
  output M_AXI_awvalid;
  output M_AXI_bready;
  input [1:0]M_AXI_bresp;
  input M_AXI_bvalid;
  input [31:0]M_AXI_rdata;
  output M_AXI_rready;
  input [1:0]M_AXI_rresp;
  input M_AXI_rvalid;
  output [31:0]M_AXI_wdata;
  input M_AXI_wready;
  output [3:0]M_AXI_wstrb;
  output M_AXI_wvalid;
  input S_ACLK;
  input S_ARESETN;
  input [31:0]S_AXI_araddr;
  input [2:0]S_AXI_arprot;
  output S_AXI_arready;
  input S_AXI_arvalid;
  input [31:0]S_AXI_awaddr;
  input [2:0]S_AXI_awprot;
  output S_AXI_awready;
  input S_AXI_awvalid;
  input S_AXI_bready;
  output [1:0]S_AXI_bresp;
  output S_AXI_bvalid;
  output [31:0]S_AXI_rdata;
  input S_AXI_rready;
  output [1:0]S_AXI_rresp;
  output S_AXI_rvalid;
  input [31:0]S_AXI_wdata;
  output S_AXI_wready;
  input [3:0]S_AXI_wstrb;
  input S_AXI_wvalid;

  wire [31:0]m00_couplers_to_m00_couplers_ARADDR;
  wire [2:0]m00_couplers_to_m00_couplers_ARPROT;
  wire m00_couplers_to_m00_couplers_ARREADY;
  wire m00_couplers_to_m00_couplers_ARVALID;
  wire [31:0]m00_couplers_to_m00_couplers_AWADDR;
  wire [2:0]m00_couplers_to_m00_couplers_AWPROT;
  wire m00_couplers_to_m00_couplers_AWREADY;
  wire m00_couplers_to_m00_couplers_AWVALID;
  wire m00_couplers_to_m00_couplers_BREADY;
  wire [1:0]m00_couplers_to_m00_couplers_BRESP;
  wire m00_couplers_to_m00_couplers_BVALID;
  wire [31:0]m00_couplers_to_m00_couplers_RDATA;
  wire m00_couplers_to_m00_couplers_RREADY;
  wire [1:0]m00_couplers_to_m00_couplers_RRESP;
  wire m00_couplers_to_m00_couplers_RVALID;
  wire [31:0]m00_couplers_to_m00_couplers_WDATA;
  wire m00_couplers_to_m00_couplers_WREADY;
  wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
  wire m00_couplers_to_m00_couplers_WVALID;

  assign M_AXI_araddr[31:0] = m00_couplers_to_m00_couplers_ARADDR;
  assign M_AXI_arprot[2:0] = m00_couplers_to_m00_couplers_ARPROT;
  assign M_AXI_arvalid = m00_couplers_to_m00_couplers_ARVALID;
  assign M_AXI_awaddr[31:0] = m00_couplers_to_m00_couplers_AWADDR;
  assign M_AXI_awprot[2:0] = m00_couplers_to_m00_couplers_AWPROT;
  assign M_AXI_awvalid = m00_couplers_to_m00_couplers_AWVALID;
  assign M_AXI_bready = m00_couplers_to_m00_couplers_BREADY;
  assign M_AXI_rready = m00_couplers_to_m00_couplers_RREADY;
  assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
  assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
  assign M_AXI_wvalid = m00_couplers_to_m00_couplers_WVALID;
  assign S_AXI_arready = m00_couplers_to_m00_couplers_ARREADY;
  assign S_AXI_awready = m00_couplers_to_m00_couplers_AWREADY;
  assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
  assign S_AXI_bvalid = m00_couplers_to_m00_couplers_BVALID;
  assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
  assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
  assign S_AXI_rvalid = m00_couplers_to_m00_couplers_RVALID;
  assign S_AXI_wready = m00_couplers_to_m00_couplers_WREADY;
  assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[31:0];
  assign m00_couplers_to_m00_couplers_ARPROT = S_AXI_arprot[2:0];
  assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready;
  assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid;
  assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[31:0];
  assign m00_couplers_to_m00_couplers_AWPROT = S_AXI_awprot[2:0];
  assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready;
  assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid;
  assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready;
  assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
  assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid;
  assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
  assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready;
  assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
  assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid;
  assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
  assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready;
  assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
  assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid;
endmodule

module m01_couplers_imp_15DQFTV
   (M_ACLK,
    M_ARESETN,
    M_AXI_araddr,
    M_AXI_arprot,
    M_AXI_arready,
    M_AXI_arvalid,
    M_AXI_awaddr,
    M_AXI_awprot,
    M_AXI_awready,
    M_AXI_awvalid,
    M_AXI_bready,
    M_AXI_bresp,
    M_AXI_bvalid,
    M_AXI_rdata,
    M_AXI_rready,
    M_AXI_rresp,
    M_AXI_rvalid,
    M_AXI_wdata,
    M_AXI_wready,
    M_AXI_wstrb,
    M_AXI_wvalid,
    S_ACLK,
    S_ARESETN,
    S_AXI_araddr,
    S_AXI_arprot,
    S_AXI_arready,
    S_AXI_arvalid,
    S_AXI_awaddr,
    S_AXI_awprot,
    S_AXI_awready,
    S_AXI_awvalid,
    S_AXI_bready,
    S_AXI_bresp,
    S_AXI_bvalid,
    S_AXI_rdata,
    S_AXI_rready,
    S_AXI_rresp,
    S_AXI_rvalid,
    S_AXI_wdata,
    S_AXI_wready,
    S_AXI_wstrb,
    S_AXI_wvalid);
  input M_ACLK;
  input M_ARESETN;
  output [31:0]M_AXI_araddr;
  output [2:0]M_AXI_arprot;
  input M_AXI_arready;
  output M_AXI_arvalid;
  output [31:0]M_AXI_awaddr;
  output [2:0]M_AXI_awprot;
  input M_AXI_awready;
  output M_AXI_awvalid;
  output M_AXI_bready;
  input [1:0]M_AXI_bresp;
  input M_AXI_bvalid;
  input [31:0]M_AXI_rdata;
  output M_AXI_rready;
  input [1:0]M_AXI_rresp;
  input M_AXI_rvalid;
  output [31:0]M_AXI_wdata;
  input M_AXI_wready;
  output [3:0]M_AXI_wstrb;
  output M_AXI_wvalid;
  input S_ACLK;
  input S_ARESETN;
  input [31:0]S_AXI_araddr;
  input [2:0]S_AXI_arprot;
  output S_AXI_arready;
  input S_AXI_arvalid;
  input [31:0]S_AXI_awaddr;
  input [2:0]S_AXI_awprot;
  output S_AXI_awready;
  input S_AXI_awvalid;
  input S_AXI_bready;
  output [1:0]S_AXI_bresp;
  output S_AXI_bvalid;
  output [31:0]S_AXI_rdata;
  input S_AXI_rready;
  output [1:0]S_AXI_rresp;
  output S_AXI_rvalid;
  input [31:0]S_AXI_wdata;
  output S_AXI_wready;
  input [3:0]S_AXI_wstrb;
  input S_AXI_wvalid;

  wire [31:0]m01_couplers_to_m01_couplers_ARADDR;
  wire [2:0]m01_couplers_to_m01_couplers_ARPROT;
  wire m01_couplers_to_m01_couplers_ARREADY;
  wire m01_couplers_to_m01_couplers_ARVALID;
  wire [31:0]m01_couplers_to_m01_couplers_AWADDR;
  wire [2:0]m01_couplers_to_m01_couplers_AWPROT;
  wire m01_couplers_to_m01_couplers_AWREADY;
  wire m01_couplers_to_m01_couplers_AWVALID;
  wire m01_couplers_to_m01_couplers_BREADY;
  wire [1:0]m01_couplers_to_m01_couplers_BRESP;
  wire m01_couplers_to_m01_couplers_BVALID;
  wire [31:0]m01_couplers_to_m01_couplers_RDATA;
  wire m01_couplers_to_m01_couplers_RREADY;
  wire [1:0]m01_couplers_to_m01_couplers_RRESP;
  wire m01_couplers_to_m01_couplers_RVALID;
  wire [31:0]m01_couplers_to_m01_couplers_WDATA;
  wire m01_couplers_to_m01_couplers_WREADY;
  wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
  wire m01_couplers_to_m01_couplers_WVALID;

  assign M_AXI_araddr[31:0] = m01_couplers_to_m01_couplers_ARADDR;
  assign M_AXI_arprot[2:0] = m01_couplers_to_m01_couplers_ARPROT;
  assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
  assign M_AXI_awaddr[31:0] = m01_couplers_to_m01_couplers_AWADDR;
  assign M_AXI_awprot[2:0] = m01_couplers_to_m01_couplers_AWPROT;
  assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
  assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
  assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
  assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
  assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
  assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
  assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
  assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
  assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
  assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
  assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
  assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
  assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
  assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
  assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[31:0];
  assign m01_couplers_to_m01_couplers_ARPROT = S_AXI_arprot[2:0];
  assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
  assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
  assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[31:0];
  assign m01_couplers_to_m01_couplers_AWPROT = S_AXI_awprot[2:0];
  assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
  assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
  assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
  assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
  assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
  assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
  assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
  assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
  assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
  assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
  assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
  assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
  assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule

(* CORE_GENERATION_INFO = "risc_axi_v5_top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=risc_axi_v5_top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=9,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=3,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=4,da_board_cnt=1,synth_mode=Global}" *) (* HW_HANDOFF = "risc_axi_v5_top.hwdef" *) 
module risc_axi_v5_top
   (key,
    led,
    nwReset,
    uart_rx,
    uart_tx,
    wClk);
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.KEY DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.KEY, LAYERED_METADATA undef" *) input [2:0]key;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.LED DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.LED, LAYERED_METADATA undef" *) output [3:0]led;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.NWRESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.NWRESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input nwReset;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.UART_RX DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.UART_RX, LAYERED_METADATA undef" *) input uart_rx;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.UART_TX DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.UART_TX, LAYERED_METADATA undef" *) output uart_tx;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.WCLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.WCLK, CLK_DOMAIN risc_axi_v5_top_wClk, FREQ_HZ 50000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input wClk;

  wire hdl4se_uart_ctrl_axi_0_uart_tx;
  wire [2:0]key_1;
  wire [3:0]led_key_0_led;
  wire nwReset_1;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M00_AXI_ARADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_M00_AXI_ARPROT;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_ARREADY;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_ARVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M00_AXI_AWADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_M00_AXI_AWPROT;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_AWREADY;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_AWVALID;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_BREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_M00_AXI_BRESP;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_BVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M00_AXI_RDATA;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_RREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_M00_AXI_RRESP;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_RVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M00_AXI_WDATA;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_WREADY;
  wire [3:0]riscv_core_with_axi_0_axi_periph_M00_AXI_WSTRB;
  wire riscv_core_with_axi_0_axi_periph_M00_AXI_WVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M01_AXI_ARADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_M01_AXI_ARPROT;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_ARREADY;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_ARVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M01_AXI_AWADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_M01_AXI_AWPROT;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_AWREADY;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_AWVALID;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_BREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_M01_AXI_BRESP;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_BVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M01_AXI_RDATA;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_RREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_M01_AXI_RRESP;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_RVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_M01_AXI_WDATA;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY;
  wire [3:0]riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB;
  wire riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID;
  wire [31:0]riscv_core_with_axi_0_m00_axi_ARADDR;
  wire [2:0]riscv_core_with_axi_0_m00_axi_ARPROT;
  wire riscv_core_with_axi_0_m00_axi_ARREADY;
  wire riscv_core_with_axi_0_m00_axi_ARVALID;
  wire [31:0]riscv_core_with_axi_0_m00_axi_AWADDR;
  wire [2:0]riscv_core_with_axi_0_m00_axi_AWPROT;
  wire riscv_core_with_axi_0_m00_axi_AWREADY;
  wire riscv_core_with_axi_0_m00_axi_AWVALID;
  wire riscv_core_with_axi_0_m00_axi_BREADY;
  wire [1:0]riscv_core_with_axi_0_m00_axi_BRESP;
  wire riscv_core_with_axi_0_m00_axi_BVALID;
  wire [31:0]riscv_core_with_axi_0_m00_axi_RDATA;
  wire riscv_core_with_axi_0_m00_axi_RREADY;
  wire [1:0]riscv_core_with_axi_0_m00_axi_RRESP;
  wire riscv_core_with_axi_0_m00_axi_RVALID;
  wire [31:0]riscv_core_with_axi_0_m00_axi_WDATA;
  wire riscv_core_with_axi_0_m00_axi_WREADY;
  wire [3:0]riscv_core_with_axi_0_m00_axi_WSTRB;
  wire riscv_core_with_axi_0_m00_axi_WVALID;
  wire [0:0]rst_wClk_50M_peripheral_aresetn;
  wire uart_rx_1;
  wire wClk_1;

  assign key_1 = key[2:0];
  assign led[3:0] = led_key_0_led;
  assign nwReset_1 = nwReset;
  assign uart_rx_1 = uart_rx;
  assign uart_tx = hdl4se_uart_ctrl_axi_0_uart_tx;
  assign wClk_1 = wClk;
  risc_axi_v5_top_hdl4se_uart_ctrl_axi_0_0 hdl4se_uart_ctrl_axi_0
       (.s00_axi_aclk(wClk_1),
        .s00_axi_araddr(riscv_core_with_axi_0_axi_periph_M00_AXI_ARADDR[3:0]),
        .s00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
        .s00_axi_arprot(riscv_core_with_axi_0_axi_periph_M00_AXI_ARPROT),
        .s00_axi_arready(riscv_core_with_axi_0_axi_periph_M00_AXI_ARREADY),
        .s00_axi_arvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_ARVALID),
        .s00_axi_awaddr(riscv_core_with_axi_0_axi_periph_M00_AXI_AWADDR[3:0]),
        .s00_axi_awprot(riscv_core_with_axi_0_axi_periph_M00_AXI_AWPROT),
        .s00_axi_awready(riscv_core_with_axi_0_axi_periph_M00_AXI_AWREADY),
        .s00_axi_awvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_AWVALID),
        .s00_axi_bready(riscv_core_with_axi_0_axi_periph_M00_AXI_BREADY),
        .s00_axi_bresp(riscv_core_with_axi_0_axi_periph_M00_AXI_BRESP),
        .s00_axi_bvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_BVALID),
        .s00_axi_rdata(riscv_core_with_axi_0_axi_periph_M00_AXI_RDATA),
        .s00_axi_rready(riscv_core_with_axi_0_axi_periph_M00_AXI_RREADY),
        .s00_axi_rresp(riscv_core_with_axi_0_axi_periph_M00_AXI_RRESP),
        .s00_axi_rvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_RVALID),
        .s00_axi_wdata(riscv_core_with_axi_0_axi_periph_M00_AXI_WDATA),
        .s00_axi_wready(riscv_core_with_axi_0_axi_periph_M00_AXI_WREADY),
        .s00_axi_wstrb(riscv_core_with_axi_0_axi_periph_M00_AXI_WSTRB),
        .s00_axi_wvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_WVALID),
        .uart_rx(uart_rx_1),
        .uart_tx(hdl4se_uart_ctrl_axi_0_uart_tx));
  risc_axi_v5_top_led_key_0_0 led_key_0
       (.key(key_1),
        .led(led_key_0_led),
        .s00_axi_aclk(wClk_1),
        .s00_axi_araddr(riscv_core_with_axi_0_axi_periph_M01_AXI_ARADDR[3:0]),
        .s00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
        .s00_axi_arprot(riscv_core_with_axi_0_axi_periph_M01_AXI_ARPROT),
        .s00_axi_arready(riscv_core_with_axi_0_axi_periph_M01_AXI_ARREADY),
        .s00_axi_arvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_ARVALID),
        .s00_axi_awaddr(riscv_core_with_axi_0_axi_periph_M01_AXI_AWADDR[3:0]),
        .s00_axi_awprot(riscv_core_with_axi_0_axi_periph_M01_AXI_AWPROT),
        .s00_axi_awready(riscv_core_with_axi_0_axi_periph_M01_AXI_AWREADY),
        .s00_axi_awvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_AWVALID),
        .s00_axi_bready(riscv_core_with_axi_0_axi_periph_M01_AXI_BREADY),
        .s00_axi_bresp(riscv_core_with_axi_0_axi_periph_M01_AXI_BRESP),
        .s00_axi_bvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_BVALID),
        .s00_axi_rdata(riscv_core_with_axi_0_axi_periph_M01_AXI_RDATA),
        .s00_axi_rready(riscv_core_with_axi_0_axi_periph_M01_AXI_RREADY),
        .s00_axi_rresp(riscv_core_with_axi_0_axi_periph_M01_AXI_RRESP),
        .s00_axi_rvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_RVALID),
        .s00_axi_wdata(riscv_core_with_axi_0_axi_periph_M01_AXI_WDATA),
        .s00_axi_wready(riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY),
        .s00_axi_wstrb(riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB),
        .s00_axi_wvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID));
  risc_axi_v5_top_riscv_core_with_axi_0_0 riscv_core_with_axi_0
       (.m00_axi_aclk(wClk_1),
        .m00_axi_araddr(riscv_core_with_axi_0_m00_axi_ARADDR),
        .m00_axi_aresetn(rst_wClk_50M_peripheral_aresetn),
        .m00_axi_arprot(riscv_core_with_axi_0_m00_axi_ARPROT),
        .m00_axi_arready(riscv_core_with_axi_0_m00_axi_ARREADY),
        .m00_axi_arvalid(riscv_core_with_axi_0_m00_axi_ARVALID),
        .m00_axi_awaddr(riscv_core_with_axi_0_m00_axi_AWADDR),
        .m00_axi_awprot(riscv_core_with_axi_0_m00_axi_AWPROT),
        .m00_axi_awready(riscv_core_with_axi_0_m00_axi_AWREADY),
        .m00_axi_awvalid(riscv_core_with_axi_0_m00_axi_AWVALID),
        .m00_axi_bready(riscv_core_with_axi_0_m00_axi_BREADY),
        .m00_axi_bresp(riscv_core_with_axi_0_m00_axi_BRESP),
        .m00_axi_bvalid(riscv_core_with_axi_0_m00_axi_BVALID),
        .m00_axi_rdata(riscv_core_with_axi_0_m00_axi_RDATA),
        .m00_axi_rready(riscv_core_with_axi_0_m00_axi_RREADY),
        .m00_axi_rresp(riscv_core_with_axi_0_m00_axi_RRESP),
        .m00_axi_rvalid(riscv_core_with_axi_0_m00_axi_RVALID),
        .m00_axi_wdata(riscv_core_with_axi_0_m00_axi_WDATA),
        .m00_axi_wready(riscv_core_with_axi_0_m00_axi_WREADY),
        .m00_axi_wstrb(riscv_core_with_axi_0_m00_axi_WSTRB),
        .m00_axi_wvalid(riscv_core_with_axi_0_m00_axi_WVALID));
  risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0 riscv_core_with_axi_0_axi_periph
       (.ACLK(wClk_1),
        .ARESETN(rst_wClk_50M_peripheral_aresetn),
        .M00_ACLK(wClk_1),
        .M00_ARESETN(rst_wClk_50M_peripheral_aresetn),
        .M00_AXI_araddr(riscv_core_with_axi_0_axi_periph_M00_AXI_ARADDR),
        .M00_AXI_arprot(riscv_core_with_axi_0_axi_periph_M00_AXI_ARPROT),
        .M00_AXI_arready(riscv_core_with_axi_0_axi_periph_M00_AXI_ARREADY),
        .M00_AXI_arvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_ARVALID),
        .M00_AXI_awaddr(riscv_core_with_axi_0_axi_periph_M00_AXI_AWADDR),
        .M00_AXI_awprot(riscv_core_with_axi_0_axi_periph_M00_AXI_AWPROT),
        .M00_AXI_awready(riscv_core_with_axi_0_axi_periph_M00_AXI_AWREADY),
        .M00_AXI_awvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_AWVALID),
        .M00_AXI_bready(riscv_core_with_axi_0_axi_periph_M00_AXI_BREADY),
        .M00_AXI_bresp(riscv_core_with_axi_0_axi_periph_M00_AXI_BRESP),
        .M00_AXI_bvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_BVALID),
        .M00_AXI_rdata(riscv_core_with_axi_0_axi_periph_M00_AXI_RDATA),
        .M00_AXI_rready(riscv_core_with_axi_0_axi_periph_M00_AXI_RREADY),
        .M00_AXI_rresp(riscv_core_with_axi_0_axi_periph_M00_AXI_RRESP),
        .M00_AXI_rvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_RVALID),
        .M00_AXI_wdata(riscv_core_with_axi_0_axi_periph_M00_AXI_WDATA),
        .M00_AXI_wready(riscv_core_with_axi_0_axi_periph_M00_AXI_WREADY),
        .M00_AXI_wstrb(riscv_core_with_axi_0_axi_periph_M00_AXI_WSTRB),
        .M00_AXI_wvalid(riscv_core_with_axi_0_axi_periph_M00_AXI_WVALID),
        .M01_ACLK(wClk_1),
        .M01_ARESETN(rst_wClk_50M_peripheral_aresetn),
        .M01_AXI_araddr(riscv_core_with_axi_0_axi_periph_M01_AXI_ARADDR),
        .M01_AXI_arprot(riscv_core_with_axi_0_axi_periph_M01_AXI_ARPROT),
        .M01_AXI_arready(riscv_core_with_axi_0_axi_periph_M01_AXI_ARREADY),
        .M01_AXI_arvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_ARVALID),
        .M01_AXI_awaddr(riscv_core_with_axi_0_axi_periph_M01_AXI_AWADDR),
        .M01_AXI_awprot(riscv_core_with_axi_0_axi_periph_M01_AXI_AWPROT),
        .M01_AXI_awready(riscv_core_with_axi_0_axi_periph_M01_AXI_AWREADY),
        .M01_AXI_awvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_AWVALID),
        .M01_AXI_bready(riscv_core_with_axi_0_axi_periph_M01_AXI_BREADY),
        .M01_AXI_bresp(riscv_core_with_axi_0_axi_periph_M01_AXI_BRESP),
        .M01_AXI_bvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_BVALID),
        .M01_AXI_rdata(riscv_core_with_axi_0_axi_periph_M01_AXI_RDATA),
        .M01_AXI_rready(riscv_core_with_axi_0_axi_periph_M01_AXI_RREADY),
        .M01_AXI_rresp(riscv_core_with_axi_0_axi_periph_M01_AXI_RRESP),
        .M01_AXI_rvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_RVALID),
        .M01_AXI_wdata(riscv_core_with_axi_0_axi_periph_M01_AXI_WDATA),
        .M01_AXI_wready(riscv_core_with_axi_0_axi_periph_M01_AXI_WREADY),
        .M01_AXI_wstrb(riscv_core_with_axi_0_axi_periph_M01_AXI_WSTRB),
        .M01_AXI_wvalid(riscv_core_with_axi_0_axi_periph_M01_AXI_WVALID),
        .S00_ACLK(wClk_1),
        .S00_ARESETN(rst_wClk_50M_peripheral_aresetn),
        .S00_AXI_araddr(riscv_core_with_axi_0_m00_axi_ARADDR),
        .S00_AXI_arprot(riscv_core_with_axi_0_m00_axi_ARPROT),
        .S00_AXI_arready(riscv_core_with_axi_0_m00_axi_ARREADY),
        .S00_AXI_arvalid(riscv_core_with_axi_0_m00_axi_ARVALID),
        .S00_AXI_awaddr(riscv_core_with_axi_0_m00_axi_AWADDR),
        .S00_AXI_awprot(riscv_core_with_axi_0_m00_axi_AWPROT),
        .S00_AXI_awready(riscv_core_with_axi_0_m00_axi_AWREADY),
        .S00_AXI_awvalid(riscv_core_with_axi_0_m00_axi_AWVALID),
        .S00_AXI_bready(riscv_core_with_axi_0_m00_axi_BREADY),
        .S00_AXI_bresp(riscv_core_with_axi_0_m00_axi_BRESP),
        .S00_AXI_bvalid(riscv_core_with_axi_0_m00_axi_BVALID),
        .S00_AXI_rdata(riscv_core_with_axi_0_m00_axi_RDATA),
        .S00_AXI_rready(riscv_core_with_axi_0_m00_axi_RREADY),
        .S00_AXI_rresp(riscv_core_with_axi_0_m00_axi_RRESP),
        .S00_AXI_rvalid(riscv_core_with_axi_0_m00_axi_RVALID),
        .S00_AXI_wdata(riscv_core_with_axi_0_m00_axi_WDATA),
        .S00_AXI_wready(riscv_core_with_axi_0_m00_axi_WREADY),
        .S00_AXI_wstrb(riscv_core_with_axi_0_m00_axi_WSTRB),
        .S00_AXI_wvalid(riscv_core_with_axi_0_m00_axi_WVALID));
  risc_axi_v5_top_rst_wClk_50M_0 rst_wClk_50M
       (.aux_reset_in(1'b1),
        .dcm_locked(1'b1),
        .ext_reset_in(nwReset_1),
        .mb_debug_sys_rst(1'b0),
        .peripheral_aresetn(rst_wClk_50M_peripheral_aresetn),
        .slowest_sync_clk(wClk_1));
endmodule

module risc_axi_v5_top_riscv_core_with_axi_0_axi_periph_0
   (ACLK,
    ARESETN,
    M00_ACLK,
    M00_ARESETN,
    M00_AXI_araddr,
    M00_AXI_arprot,
    M00_AXI_arready,
    M00_AXI_arvalid,
    M00_AXI_awaddr,
    M00_AXI_awprot,
    M00_AXI_awready,
    M00_AXI_awvalid,
    M00_AXI_bready,
    M00_AXI_bresp,
    M00_AXI_bvalid,
    M00_AXI_rdata,
    M00_AXI_rready,
    M00_AXI_rresp,
    M00_AXI_rvalid,
    M00_AXI_wdata,
    M00_AXI_wready,
    M00_AXI_wstrb,
    M00_AXI_wvalid,
    M01_ACLK,
    M01_ARESETN,
    M01_AXI_araddr,
    M01_AXI_arprot,
    M01_AXI_arready,
    M01_AXI_arvalid,
    M01_AXI_awaddr,
    M01_AXI_awprot,
    M01_AXI_awready,
    M01_AXI_awvalid,
    M01_AXI_bready,
    M01_AXI_bresp,
    M01_AXI_bvalid,
    M01_AXI_rdata,
    M01_AXI_rready,
    M01_AXI_rresp,
    M01_AXI_rvalid,
    M01_AXI_wdata,
    M01_AXI_wready,
    M01_AXI_wstrb,
    M01_AXI_wvalid,
    S00_ACLK,
    S00_ARESETN,
    S00_AXI_araddr,
    S00_AXI_arprot,
    S00_AXI_arready,
    S00_AXI_arvalid,
    S00_AXI_awaddr,
    S00_AXI_awprot,
    S00_AXI_awready,
    S00_AXI_awvalid,
    S00_AXI_bready,
    S00_AXI_bresp,
    S00_AXI_bvalid,
    S00_AXI_rdata,
    S00_AXI_rready,
    S00_AXI_rresp,
    S00_AXI_rvalid,
    S00_AXI_wdata,
    S00_AXI_wready,
    S00_AXI_wstrb,
    S00_AXI_wvalid);
  input ACLK;
  input ARESETN;
  input M00_ACLK;
  input M00_ARESETN;
  output [31:0]M00_AXI_araddr;
  output [2:0]M00_AXI_arprot;
  input M00_AXI_arready;
  output M00_AXI_arvalid;
  output [31:0]M00_AXI_awaddr;
  output [2:0]M00_AXI_awprot;
  input M00_AXI_awready;
  output M00_AXI_awvalid;
  output M00_AXI_bready;
  input [1:0]M00_AXI_bresp;
  input M00_AXI_bvalid;
  input [31:0]M00_AXI_rdata;
  output M00_AXI_rready;
  input [1:0]M00_AXI_rresp;
  input M00_AXI_rvalid;
  output [31:0]M00_AXI_wdata;
  input M00_AXI_wready;
  output [3:0]M00_AXI_wstrb;
  output M00_AXI_wvalid;
  input M01_ACLK;
  input M01_ARESETN;
  output [31:0]M01_AXI_araddr;
  output [2:0]M01_AXI_arprot;
  input M01_AXI_arready;
  output M01_AXI_arvalid;
  output [31:0]M01_AXI_awaddr;
  output [2:0]M01_AXI_awprot;
  input M01_AXI_awready;
  output M01_AXI_awvalid;
  output M01_AXI_bready;
  input [1:0]M01_AXI_bresp;
  input M01_AXI_bvalid;
  input [31:0]M01_AXI_rdata;
  output M01_AXI_rready;
  input [1:0]M01_AXI_rresp;
  input M01_AXI_rvalid;
  output [31:0]M01_AXI_wdata;
  input M01_AXI_wready;
  output [3:0]M01_AXI_wstrb;
  output M01_AXI_wvalid;
  input S00_ACLK;
  input S00_ARESETN;
  input [31:0]S00_AXI_araddr;
  input [2:0]S00_AXI_arprot;
  output S00_AXI_arready;
  input S00_AXI_arvalid;
  input [31:0]S00_AXI_awaddr;
  input [2:0]S00_AXI_awprot;
  output S00_AXI_awready;
  input S00_AXI_awvalid;
  input S00_AXI_bready;
  output [1:0]S00_AXI_bresp;
  output S00_AXI_bvalid;
  output [31:0]S00_AXI_rdata;
  input S00_AXI_rready;
  output [1:0]S00_AXI_rresp;
  output S00_AXI_rvalid;
  input [31:0]S00_AXI_wdata;
  output S00_AXI_wready;
  input [3:0]S00_AXI_wstrb;
  input S00_AXI_wvalid;

  wire [31:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR;
  wire [2:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID;
  wire [31:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR;
  wire [2:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY;
  wire [1:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID;
  wire [31:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY;
  wire [1:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID;
  wire [31:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY;
  wire [3:0]m00_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB;
  wire m00_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID;
  wire [31:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR;
  wire [2:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID;
  wire [31:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR;
  wire [2:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY;
  wire [1:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID;
  wire [31:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY;
  wire [1:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID;
  wire [31:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY;
  wire [3:0]m01_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB;
  wire m01_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID;
  wire riscv_core_with_axi_0_axi_periph_ACLK_net;
  wire riscv_core_with_axi_0_axi_periph_ARESETN_net;
  wire [31:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARPROT;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARREADY;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWADDR;
  wire [2:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWPROT;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWREADY;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWVALID;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_BREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_BRESP;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_BVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_RDATA;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_RREADY;
  wire [1:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_RRESP;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_RVALID;
  wire [31:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_WDATA;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_WREADY;
  wire [3:0]riscv_core_with_axi_0_axi_periph_to_s00_couplers_WSTRB;
  wire riscv_core_with_axi_0_axi_periph_to_s00_couplers_WVALID;
  wire [31:0]s00_couplers_to_xbar_ARADDR;
  wire [2:0]s00_couplers_to_xbar_ARPROT;
  wire [0:0]s00_couplers_to_xbar_ARREADY;
  wire s00_couplers_to_xbar_ARVALID;
  wire [31:0]s00_couplers_to_xbar_AWADDR;
  wire [2:0]s00_couplers_to_xbar_AWPROT;
  wire [0:0]s00_couplers_to_xbar_AWREADY;
  wire s00_couplers_to_xbar_AWVALID;
  wire s00_couplers_to_xbar_BREADY;
  wire [1:0]s00_couplers_to_xbar_BRESP;
  wire [0:0]s00_couplers_to_xbar_BVALID;
  wire [31:0]s00_couplers_to_xbar_RDATA;
  wire s00_couplers_to_xbar_RREADY;
  wire [1:0]s00_couplers_to_xbar_RRESP;
  wire [0:0]s00_couplers_to_xbar_RVALID;
  wire [31:0]s00_couplers_to_xbar_WDATA;
  wire [0:0]s00_couplers_to_xbar_WREADY;
  wire [3:0]s00_couplers_to_xbar_WSTRB;
  wire s00_couplers_to_xbar_WVALID;
  wire [31:0]xbar_to_m00_couplers_ARADDR;
  wire [2:0]xbar_to_m00_couplers_ARPROT;
  wire xbar_to_m00_couplers_ARREADY;
  wire [0:0]xbar_to_m00_couplers_ARVALID;
  wire [31:0]xbar_to_m00_couplers_AWADDR;
  wire [2:0]xbar_to_m00_couplers_AWPROT;
  wire xbar_to_m00_couplers_AWREADY;
  wire [0:0]xbar_to_m00_couplers_AWVALID;
  wire [0:0]xbar_to_m00_couplers_BREADY;
  wire [1:0]xbar_to_m00_couplers_BRESP;
  wire xbar_to_m00_couplers_BVALID;
  wire [31:0]xbar_to_m00_couplers_RDATA;
  wire [0:0]xbar_to_m00_couplers_RREADY;
  wire [1:0]xbar_to_m00_couplers_RRESP;
  wire xbar_to_m00_couplers_RVALID;
  wire [31:0]xbar_to_m00_couplers_WDATA;
  wire xbar_to_m00_couplers_WREADY;
  wire [3:0]xbar_to_m00_couplers_WSTRB;
  wire [0:0]xbar_to_m00_couplers_WVALID;
  wire [63:32]xbar_to_m01_couplers_ARADDR;
  wire [5:3]xbar_to_m01_couplers_ARPROT;
  wire xbar_to_m01_couplers_ARREADY;
  wire [1:1]xbar_to_m01_couplers_ARVALID;
  wire [63:32]xbar_to_m01_couplers_AWADDR;
  wire [5:3]xbar_to_m01_couplers_AWPROT;
  wire xbar_to_m01_couplers_AWREADY;
  wire [1:1]xbar_to_m01_couplers_AWVALID;
  wire [1:1]xbar_to_m01_couplers_BREADY;
  wire [1:0]xbar_to_m01_couplers_BRESP;
  wire xbar_to_m01_couplers_BVALID;
  wire [31:0]xbar_to_m01_couplers_RDATA;
  wire [1:1]xbar_to_m01_couplers_RREADY;
  wire [1:0]xbar_to_m01_couplers_RRESP;
  wire xbar_to_m01_couplers_RVALID;
  wire [63:32]xbar_to_m01_couplers_WDATA;
  wire xbar_to_m01_couplers_WREADY;
  wire [7:4]xbar_to_m01_couplers_WSTRB;
  wire [1:1]xbar_to_m01_couplers_WVALID;

  assign M00_AXI_araddr[31:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR;
  assign M00_AXI_arprot[2:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT;
  assign M00_AXI_arvalid = m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID;
  assign M00_AXI_awaddr[31:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR;
  assign M00_AXI_awprot[2:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT;
  assign M00_AXI_awvalid = m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID;
  assign M00_AXI_bready = m00_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY;
  assign M00_AXI_rready = m00_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY;
  assign M00_AXI_wdata[31:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA;
  assign M00_AXI_wstrb[3:0] = m00_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB;
  assign M00_AXI_wvalid = m00_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID;
  assign M01_AXI_araddr[31:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR;
  assign M01_AXI_arprot[2:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT;
  assign M01_AXI_arvalid = m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID;
  assign M01_AXI_awaddr[31:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR;
  assign M01_AXI_awprot[2:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT;
  assign M01_AXI_awvalid = m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID;
  assign M01_AXI_bready = m01_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY;
  assign M01_AXI_rready = m01_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY;
  assign M01_AXI_wdata[31:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA;
  assign M01_AXI_wstrb[3:0] = m01_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB;
  assign M01_AXI_wvalid = m01_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID;
  assign S00_AXI_arready = riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARREADY;
  assign S00_AXI_awready = riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWREADY;
  assign S00_AXI_bresp[1:0] = riscv_core_with_axi_0_axi_periph_to_s00_couplers_BRESP;
  assign S00_AXI_bvalid = riscv_core_with_axi_0_axi_periph_to_s00_couplers_BVALID;
  assign S00_AXI_rdata[31:0] = riscv_core_with_axi_0_axi_periph_to_s00_couplers_RDATA;
  assign S00_AXI_rresp[1:0] = riscv_core_with_axi_0_axi_periph_to_s00_couplers_RRESP;
  assign S00_AXI_rvalid = riscv_core_with_axi_0_axi_periph_to_s00_couplers_RVALID;
  assign S00_AXI_wready = riscv_core_with_axi_0_axi_periph_to_s00_couplers_WREADY;
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY = M00_AXI_arready;
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY = M00_AXI_awready;
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID = M00_AXI_bvalid;
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID = M00_AXI_rvalid;
  assign m00_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY = M00_AXI_wready;
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY = M01_AXI_arready;
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY = M01_AXI_awready;
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID = M01_AXI_bvalid;
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID = M01_AXI_rvalid;
  assign m01_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY = M01_AXI_wready;
  assign riscv_core_with_axi_0_axi_periph_ACLK_net = ACLK;
  assign riscv_core_with_axi_0_axi_periph_ARESETN_net = ARESETN;
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
  assign riscv_core_with_axi_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
  m00_couplers_imp_DIBHKD m00_couplers
       (.M_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .M_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .M_AXI_araddr(m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR),
        .M_AXI_arprot(m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT),
        .M_AXI_arready(m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY),
        .M_AXI_arvalid(m00_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID),
        .M_AXI_awaddr(m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR),
        .M_AXI_awprot(m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT),
        .M_AXI_awready(m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY),
        .M_AXI_awvalid(m00_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID),
        .M_AXI_bready(m00_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY),
        .M_AXI_bresp(m00_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP),
        .M_AXI_bvalid(m00_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID),
        .M_AXI_rdata(m00_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA),
        .M_AXI_rready(m00_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY),
        .M_AXI_rresp(m00_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP),
        .M_AXI_rvalid(m00_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID),
        .M_AXI_wdata(m00_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA),
        .M_AXI_wready(m00_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY),
        .M_AXI_wstrb(m00_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB),
        .M_AXI_wvalid(m00_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID),
        .S_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .S_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
        .S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
        .S_AXI_arready(xbar_to_m00_couplers_ARREADY),
        .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
        .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
        .S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
        .S_AXI_awready(xbar_to_m00_couplers_AWREADY),
        .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
        .S_AXI_bready(xbar_to_m00_couplers_BREADY),
        .S_AXI_bresp(xbar_to_m00_couplers_BRESP),
        .S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
        .S_AXI_rdata(xbar_to_m00_couplers_RDATA),
        .S_AXI_rready(xbar_to_m00_couplers_RREADY),
        .S_AXI_rresp(xbar_to_m00_couplers_RRESP),
        .S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
        .S_AXI_wdata(xbar_to_m00_couplers_WDATA),
        .S_AXI_wready(xbar_to_m00_couplers_WREADY),
        .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
        .S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
  m01_couplers_imp_15DQFTV m01_couplers
       (.M_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .M_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .M_AXI_araddr(m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARADDR),
        .M_AXI_arprot(m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARPROT),
        .M_AXI_arready(m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARREADY),
        .M_AXI_arvalid(m01_couplers_to_riscv_core_with_axi_0_axi_periph_ARVALID),
        .M_AXI_awaddr(m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWADDR),
        .M_AXI_awprot(m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWPROT),
        .M_AXI_awready(m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWREADY),
        .M_AXI_awvalid(m01_couplers_to_riscv_core_with_axi_0_axi_periph_AWVALID),
        .M_AXI_bready(m01_couplers_to_riscv_core_with_axi_0_axi_periph_BREADY),
        .M_AXI_bresp(m01_couplers_to_riscv_core_with_axi_0_axi_periph_BRESP),
        .M_AXI_bvalid(m01_couplers_to_riscv_core_with_axi_0_axi_periph_BVALID),
        .M_AXI_rdata(m01_couplers_to_riscv_core_with_axi_0_axi_periph_RDATA),
        .M_AXI_rready(m01_couplers_to_riscv_core_with_axi_0_axi_periph_RREADY),
        .M_AXI_rresp(m01_couplers_to_riscv_core_with_axi_0_axi_periph_RRESP),
        .M_AXI_rvalid(m01_couplers_to_riscv_core_with_axi_0_axi_periph_RVALID),
        .M_AXI_wdata(m01_couplers_to_riscv_core_with_axi_0_axi_periph_WDATA),
        .M_AXI_wready(m01_couplers_to_riscv_core_with_axi_0_axi_periph_WREADY),
        .M_AXI_wstrb(m01_couplers_to_riscv_core_with_axi_0_axi_periph_WSTRB),
        .M_AXI_wvalid(m01_couplers_to_riscv_core_with_axi_0_axi_periph_WVALID),
        .S_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .S_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .S_AXI_araddr(xbar_to_m01_couplers_ARADDR),
        .S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
        .S_AXI_arready(xbar_to_m01_couplers_ARREADY),
        .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
        .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR),
        .S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
        .S_AXI_awready(xbar_to_m01_couplers_AWREADY),
        .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
        .S_AXI_bready(xbar_to_m01_couplers_BREADY),
        .S_AXI_bresp(xbar_to_m01_couplers_BRESP),
        .S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
        .S_AXI_rdata(xbar_to_m01_couplers_RDATA),
        .S_AXI_rready(xbar_to_m01_couplers_RREADY),
        .S_AXI_rresp(xbar_to_m01_couplers_RRESP),
        .S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
        .S_AXI_wdata(xbar_to_m01_couplers_WDATA),
        .S_AXI_wready(xbar_to_m01_couplers_WREADY),
        .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
        .S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
  s00_couplers_imp_4FUU9H s00_couplers
       (.M_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .M_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
        .M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
        .M_AXI_arready(s00_couplers_to_xbar_ARREADY),
        .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
        .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
        .M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
        .M_AXI_awready(s00_couplers_to_xbar_AWREADY),
        .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
        .M_AXI_bready(s00_couplers_to_xbar_BREADY),
        .M_AXI_bresp(s00_couplers_to_xbar_BRESP),
        .M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
        .M_AXI_rdata(s00_couplers_to_xbar_RDATA),
        .M_AXI_rready(s00_couplers_to_xbar_RREADY),
        .M_AXI_rresp(s00_couplers_to_xbar_RRESP),
        .M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
        .M_AXI_wdata(s00_couplers_to_xbar_WDATA),
        .M_AXI_wready(s00_couplers_to_xbar_WREADY),
        .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
        .M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
        .S_ACLK(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .S_ARESETN(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .S_AXI_araddr(riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARADDR),
        .S_AXI_arprot(riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARPROT),
        .S_AXI_arready(riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARREADY),
        .S_AXI_arvalid(riscv_core_with_axi_0_axi_periph_to_s00_couplers_ARVALID),
        .S_AXI_awaddr(riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWADDR),
        .S_AXI_awprot(riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWPROT),
        .S_AXI_awready(riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWREADY),
        .S_AXI_awvalid(riscv_core_with_axi_0_axi_periph_to_s00_couplers_AWVALID),
        .S_AXI_bready(riscv_core_with_axi_0_axi_periph_to_s00_couplers_BREADY),
        .S_AXI_bresp(riscv_core_with_axi_0_axi_periph_to_s00_couplers_BRESP),
        .S_AXI_bvalid(riscv_core_with_axi_0_axi_periph_to_s00_couplers_BVALID),
        .S_AXI_rdata(riscv_core_with_axi_0_axi_periph_to_s00_couplers_RDATA),
        .S_AXI_rready(riscv_core_with_axi_0_axi_periph_to_s00_couplers_RREADY),
        .S_AXI_rresp(riscv_core_with_axi_0_axi_periph_to_s00_couplers_RRESP),
        .S_AXI_rvalid(riscv_core_with_axi_0_axi_periph_to_s00_couplers_RVALID),
        .S_AXI_wdata(riscv_core_with_axi_0_axi_periph_to_s00_couplers_WDATA),
        .S_AXI_wready(riscv_core_with_axi_0_axi_periph_to_s00_couplers_WREADY),
        .S_AXI_wstrb(riscv_core_with_axi_0_axi_periph_to_s00_couplers_WSTRB),
        .S_AXI_wvalid(riscv_core_with_axi_0_axi_periph_to_s00_couplers_WVALID));
  risc_axi_v5_top_xbar_0 xbar
       (.aclk(riscv_core_with_axi_0_axi_periph_ACLK_net),
        .aresetn(riscv_core_with_axi_0_axi_periph_ARESETN_net),
        .m_axi_araddr({xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
        .m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
        .m_axi_arready({xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
        .m_axi_arvalid({xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
        .m_axi_awaddr({xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
        .m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
        .m_axi_awready({xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
        .m_axi_awvalid({xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
        .m_axi_bready({xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
        .m_axi_bresp({xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
        .m_axi_bvalid({xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
        .m_axi_rdata({xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
        .m_axi_rready({xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
        .m_axi_rresp({xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
        .m_axi_rvalid({xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
        .m_axi_wdata({xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
        .m_axi_wready({xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
        .m_axi_wstrb({xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
        .m_axi_wvalid({xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
        .s_axi_araddr(s00_couplers_to_xbar_ARADDR),
        .s_axi_arprot(s00_couplers_to_xbar_ARPROT),
        .s_axi_arready(s00_couplers_to_xbar_ARREADY),
        .s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
        .s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
        .s_axi_awprot(s00_couplers_to_xbar_AWPROT),
        .s_axi_awready(s00_couplers_to_xbar_AWREADY),
        .s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
        .s_axi_bready(s00_couplers_to_xbar_BREADY),
        .s_axi_bresp(s00_couplers_to_xbar_BRESP),
        .s_axi_bvalid(s00_couplers_to_xbar_BVALID),
        .s_axi_rdata(s00_couplers_to_xbar_RDATA),
        .s_axi_rready(s00_couplers_to_xbar_RREADY),
        .s_axi_rresp(s00_couplers_to_xbar_RRESP),
        .s_axi_rvalid(s00_couplers_to_xbar_RVALID),
        .s_axi_wdata(s00_couplers_to_xbar_WDATA),
        .s_axi_wready(s00_couplers_to_xbar_WREADY),
        .s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
        .s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule

module s00_couplers_imp_4FUU9H
   (M_ACLK,
    M_ARESETN,
    M_AXI_araddr,
    M_AXI_arprot,
    M_AXI_arready,
    M_AXI_arvalid,
    M_AXI_awaddr,
    M_AXI_awprot,
    M_AXI_awready,
    M_AXI_awvalid,
    M_AXI_bready,
    M_AXI_bresp,
    M_AXI_bvalid,
    M_AXI_rdata,
    M_AXI_rready,
    M_AXI_rresp,
    M_AXI_rvalid,
    M_AXI_wdata,
    M_AXI_wready,
    M_AXI_wstrb,
    M_AXI_wvalid,
    S_ACLK,
    S_ARESETN,
    S_AXI_araddr,
    S_AXI_arprot,
    S_AXI_arready,
    S_AXI_arvalid,
    S_AXI_awaddr,
    S_AXI_awprot,
    S_AXI_awready,
    S_AXI_awvalid,
    S_AXI_bready,
    S_AXI_bresp,
    S_AXI_bvalid,
    S_AXI_rdata,
    S_AXI_rready,
    S_AXI_rresp,
    S_AXI_rvalid,
    S_AXI_wdata,
    S_AXI_wready,
    S_AXI_wstrb,
    S_AXI_wvalid);
  input M_ACLK;
  input M_ARESETN;
  output [31:0]M_AXI_araddr;
  output [2:0]M_AXI_arprot;
  input M_AXI_arready;
  output M_AXI_arvalid;
  output [31:0]M_AXI_awaddr;
  output [2:0]M_AXI_awprot;
  input M_AXI_awready;
  output M_AXI_awvalid;
  output M_AXI_bready;
  input [1:0]M_AXI_bresp;
  input M_AXI_bvalid;
  input [31:0]M_AXI_rdata;
  output M_AXI_rready;
  input [1:0]M_AXI_rresp;
  input M_AXI_rvalid;
  output [31:0]M_AXI_wdata;
  input M_AXI_wready;
  output [3:0]M_AXI_wstrb;
  output M_AXI_wvalid;
  input S_ACLK;
  input S_ARESETN;
  input [31:0]S_AXI_araddr;
  input [2:0]S_AXI_arprot;
  output S_AXI_arready;
  input S_AXI_arvalid;
  input [31:0]S_AXI_awaddr;
  input [2:0]S_AXI_awprot;
  output S_AXI_awready;
  input S_AXI_awvalid;
  input S_AXI_bready;
  output [1:0]S_AXI_bresp;
  output S_AXI_bvalid;
  output [31:0]S_AXI_rdata;
  input S_AXI_rready;
  output [1:0]S_AXI_rresp;
  output S_AXI_rvalid;
  input [31:0]S_AXI_wdata;
  output S_AXI_wready;
  input [3:0]S_AXI_wstrb;
  input S_AXI_wvalid;

  wire [31:0]s00_couplers_to_s00_couplers_ARADDR;
  wire [2:0]s00_couplers_to_s00_couplers_ARPROT;
  wire s00_couplers_to_s00_couplers_ARREADY;
  wire s00_couplers_to_s00_couplers_ARVALID;
  wire [31:0]s00_couplers_to_s00_couplers_AWADDR;
  wire [2:0]s00_couplers_to_s00_couplers_AWPROT;
  wire s00_couplers_to_s00_couplers_AWREADY;
  wire s00_couplers_to_s00_couplers_AWVALID;
  wire s00_couplers_to_s00_couplers_BREADY;
  wire [1:0]s00_couplers_to_s00_couplers_BRESP;
  wire s00_couplers_to_s00_couplers_BVALID;
  wire [31:0]s00_couplers_to_s00_couplers_RDATA;
  wire s00_couplers_to_s00_couplers_RREADY;
  wire [1:0]s00_couplers_to_s00_couplers_RRESP;
  wire s00_couplers_to_s00_couplers_RVALID;
  wire [31:0]s00_couplers_to_s00_couplers_WDATA;
  wire s00_couplers_to_s00_couplers_WREADY;
  wire [3:0]s00_couplers_to_s00_couplers_WSTRB;
  wire s00_couplers_to_s00_couplers_WVALID;

  assign M_AXI_araddr[31:0] = s00_couplers_to_s00_couplers_ARADDR;
  assign M_AXI_arprot[2:0] = s00_couplers_to_s00_couplers_ARPROT;
  assign M_AXI_arvalid = s00_couplers_to_s00_couplers_ARVALID;
  assign M_AXI_awaddr[31:0] = s00_couplers_to_s00_couplers_AWADDR;
  assign M_AXI_awprot[2:0] = s00_couplers_to_s00_couplers_AWPROT;
  assign M_AXI_awvalid = s00_couplers_to_s00_couplers_AWVALID;
  assign M_AXI_bready = s00_couplers_to_s00_couplers_BREADY;
  assign M_AXI_rready = s00_couplers_to_s00_couplers_RREADY;
  assign M_AXI_wdata[31:0] = s00_couplers_to_s00_couplers_WDATA;
  assign M_AXI_wstrb[3:0] = s00_couplers_to_s00_couplers_WSTRB;
  assign M_AXI_wvalid = s00_couplers_to_s00_couplers_WVALID;
  assign S_AXI_arready = s00_couplers_to_s00_couplers_ARREADY;
  assign S_AXI_awready = s00_couplers_to_s00_couplers_AWREADY;
  assign S_AXI_bresp[1:0] = s00_couplers_to_s00_couplers_BRESP;
  assign S_AXI_bvalid = s00_couplers_to_s00_couplers_BVALID;
  assign S_AXI_rdata[31:0] = s00_couplers_to_s00_couplers_RDATA;
  assign S_AXI_rresp[1:0] = s00_couplers_to_s00_couplers_RRESP;
  assign S_AXI_rvalid = s00_couplers_to_s00_couplers_RVALID;
  assign S_AXI_wready = s00_couplers_to_s00_couplers_WREADY;
  assign s00_couplers_to_s00_couplers_ARADDR = S_AXI_araddr[31:0];
  assign s00_couplers_to_s00_couplers_ARPROT = S_AXI_arprot[2:0];
  assign s00_couplers_to_s00_couplers_ARREADY = M_AXI_arready;
  assign s00_couplers_to_s00_couplers_ARVALID = S_AXI_arvalid;
  assign s00_couplers_to_s00_couplers_AWADDR = S_AXI_awaddr[31:0];
  assign s00_couplers_to_s00_couplers_AWPROT = S_AXI_awprot[2:0];
  assign s00_couplers_to_s00_couplers_AWREADY = M_AXI_awready;
  assign s00_couplers_to_s00_couplers_AWVALID = S_AXI_awvalid;
  assign s00_couplers_to_s00_couplers_BREADY = S_AXI_bready;
  assign s00_couplers_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
  assign s00_couplers_to_s00_couplers_BVALID = M_AXI_bvalid;
  assign s00_couplers_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
  assign s00_couplers_to_s00_couplers_RREADY = S_AXI_rready;
  assign s00_couplers_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
  assign s00_couplers_to_s00_couplers_RVALID = M_AXI_rvalid;
  assign s00_couplers_to_s00_couplers_WDATA = S_AXI_wdata[31:0];
  assign s00_couplers_to_s00_couplers_WREADY = M_AXI_wready;
  assign s00_couplers_to_s00_couplers_WSTRB = S_AXI_wstrb[3:0];
  assign s00_couplers_to_s00_couplers_WVALID = S_AXI_wvalid;
endmodule