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examples/hdl4se_riscv/verilog/led_key/led_key.v
浏览文件 @ 0ae6b329
......@@ -51,102 +51,102 @@
end
end
reg [3 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [3 : 0] axi_araddr;
reg axi_arready;
reg [31 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
reg [31:0] slv_reg0;
reg [31:0] slv_reg1;
reg [31:0] slv_reg2;
reg [31:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [31:0] reg_data_out;
reg aw_en;
assign s00_axi_awready = axi_awready;
assign s00_axi_wready = axi_wready;
assign s00_axi_bresp = axi_bresp;
assign s00_axi_bvalid = axi_bvalid;
assign s00_axi_arready = axi_arready;
assign s00_axi_rvalid = axi_rvalid;
assign s00_axi_rdata = axi_rdata;
assign s00_axi_rresp = axi_rresp;
reg [3:0] axi_awaddr_r;
reg axi_awvalid_r;
wire axi_awvalid = s00_axi_awvalid || axi_awvalid_r;
wire [3:0] axi_awaddr = s00_axi_awvalid ? s00_axi_awaddr : axi_awaddr_r;
reg [31:0] axi_wdata_r;
reg [3:0] axi_wstrb_r;
reg axi_wvalid_r;
wire axi_wvalid = s00_axi_wvalid || axi_wvalid_r;
wire [31:0] axi_wdata = s00_axi_wvalid ? s00_axi_wdata : axi_wdata_r;
wire [3:0] axi_wstrb = s00_axi_wvalid ? s00_axi_wstrb : axi_wstrb_r;
assign s00_axi_awready = 1;
assign s00_axi_wready = 1;
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end else if (~axi_awready && s00_axi_awvalid && s00_axi_wvalid && aw_en) begin
axi_awready <= 1'b1;
aw_en <= 1'b0;
end else if (s00_axi_bready && axi_bvalid) begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end else begin
axi_awready <= 1'b0;
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_awaddr <= 0;
end else if (~axi_awready && s00_axi_awvalid && s00_axi_wvalid && aw_en) begin
axi_awaddr <= s00_axi_awaddr;
end
end
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
end else begin
if (s00_axi_awvalid) begin
axi_awaddr_r <= s00_axi_awaddr;
end
if (s00_axi_wvalid) begin
axi_wdata_r <= s00_axi_wdata;
axi_wstrb_r <= s00_axi_wstrb;
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_wready <= 1'b0;
end else if (~axi_wready && s00_axi_wvalid && s00_axi_awvalid && aw_en ) begin
axi_wready <= 1'b1;
end else begin
axi_wready <= 1'b0;
end
end
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
axi_wvalid_r <= 0;
axi_awvalid_r <= 0;
end else begin
if (axi_awvalid && axi_wvalid) begin
axi_wvalid_r <= 0;
axi_awvalid_r <= 0;
end else if (axi_awvalid) begin
axi_awvalid_r <= 1;
end else if (axi_wvalid) begin
axi_wvalid_r <= 1;
end
end
assign slv_reg_wren = axi_wready && s00_axi_wvalid && axi_awready && s00_axi_awvalid;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
assign s00_axi_bresp = axi_bresp;
assign s00_axi_bvalid = axi_bvalid;
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
axi_bresp <= 0;
axi_bvalid <= 0;
end else if (axi_awvalid && axi_wvalid) begin
axi_bresp <= 0;
axi_bvalid <= 1;
end else begin
axi_bresp <= 0;
axi_bvalid <= 0;
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
if (~s00_axi_aresetn) begin
cpucount <= 32'hffffffff;
end else if (slv_reg_wren) begin
cpucount <= s00_axi_wdata;
end else if (axi_awvalid && axi_wvalid) begin
if (axi_awaddr == 4) begin
cpucount <= {axi_wstrb[3] ? axi_wdata[31:24] : cpucount[31:24],
axi_wstrb[2] ? axi_wdata[23:16] : cpucount[23:16],
axi_wstrb[1] ? axi_wdata[18:8] : cpucount[15:8],
axi_wstrb[0] ? axi_wdata[7:0] : cpucount[7:0]
};
end
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end else if (axi_awready && s00_axi_awvalid && ~axi_bvalid && axi_wready && s00_axi_wvalid) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end else if (s00_axi_bready && axi_bvalid) begin
axi_bvalid <= 1'b0;
end
end
reg axi_arready;
reg [3:0] axi_raddr_r;
reg axi_raddr_valid_r;
reg [31 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
wire axi_raddr_valid = s00_axi_arvalid || axi_raddr_valid_r;
wire [3:0] axi_raddr = s00_axi_arvalid ? s00_axi_araddr : axi_raddr_r;
assign s00_axi_arready = axi_arready;
assign s00_axi_rvalid = axi_rvalid;
assign s00_axi_rdata = axi_rdata;
assign s00_axi_rresp = axi_rresp;
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
if ( ~s00_axi_aresetn) begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end if (~axi_arready && s00_axi_arvalid) begin
end if (s00_axi_arvalid) begin
axi_arready <= 1'b1;
axi_araddr <= s00_axi_araddr;
axi_raddr_r <= s00_axi_araddr;
end else begin
axi_arready <= 1'b0;
end
......@@ -154,25 +154,29 @@
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end else if (axi_arready && s00_axi_arvalid && ~axi_rvalid) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end else if (axi_rvalid && s00_axi_rready) begin
axi_rvalid <= 1'b0;
end
if (~s00_axi_aresetn) begin
axi_raddr_valid_r <= 0;
end else begin
if (s00_axi_rready && axi_raddr_valid) begin
axi_raddr_valid_r <= 0;
end else if (s00_axi_arvalid) begin
axi_raddr_valid_r <= 1;
end
end
end
assign slv_reg_rden = axi_arready & s00_axi_arvalid & ~axi_rvalid;
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
if (~s00_axi_aresetn) begin
axi_rdata <= 0;
end else if (slv_reg_rden) begin
axi_rdata <= {28'h0, s00_axi_aresetn, key};
end
axi_rvalid <= 0;
end else if (axi_raddr_valid && ~axi_rvalid) begin
if (axi_raddr == 0)
axi_rdata <= {28'h0, s00_axi_aresetn, key};
axi_rvalid <= 1;
end else if (s00_axi_rready && axi_rvalid) begin
axi_rvalid <= 0;
end
end
endmodule
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_v5.v
浏览文件 @ 0ae6b329
......@@ -384,7 +384,7 @@ module riscv_core_v5(
wire [31:0] newwriteaddr = rs1 + imm;
//DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, rs1, regrddata, imm") {
always @(nwReset or state or opcode or newwriteaddr or rs2 or func3 or lastaddr or lastv) begin
always @(nwReset or state or opcode or newwriteaddr or rs2 or func3 or lastaddr or lastv or wWriteReady) begin
write = 0;
writeaddr = 0;
writemask = 0;
......
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ 0ae6b329
......@@ -89,7 +89,7 @@ module riscv_core_with_axi_master (
regfile regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);
`define ALTERA
`define ALTERA_
`ifdef ALTERA
ram4kB ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(isramwriteaddr ? wWrite : 1'b0), .q(bReadDataRam));
......@@ -175,8 +175,10 @@ module riscv_core_with_axi_master (
always @(posedge m00_axi_aclk)
if (~m00_axi_aresetn)
writeready <= 1'b0;
else if (~writeready)
writeready <= m00_axi_bvalid || write_local || isramwriteaddr;
else
writeready <= m00_axi_wready || write_local || isramwriteaddr;
writeready <= 0;
always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
begin
......
examples/hdl4se_riscv/verilog/uart/hdl4se_uart_ctrl_axi.v
浏览文件 @ 0ae6b329
......@@ -135,84 +135,142 @@ module hdl4se_uart_ctrl_axi
assign ctl_state = {28'h0, send_buf_full, send_buf_empty, recv_buf_full, ~recv_buf_empty};
/* axi bus */
reg [3:0] axi_awaddr_r;
reg axi_awvalid_r;
wire axi_awvalid = s00_axi_awvalid || axi_awvalid_r;
wire [3:0] axi_awaddr = s00_axi_awvalid ? s00_axi_awaddr : axi_awaddr_r;
reg [31:0] axi_wdata_r;
reg [3:0] axi_wstrb_r;
reg axi_wvalid_r;
wire axi_wvalid = s00_axi_wvalid || axi_wvalid_r;
wire [31:0] axi_wdata = s00_axi_wvalid ? s00_axi_wdata : axi_wdata_r;
wire [3:0] axi_wstrb = s00_axi_wvalid ? s00_axi_wstrb : axi_wstrb_r;
assign s00_axi_awready = 1;
assign s00_axi_wready = 1;
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
end else begin
if (s00_axi_awvalid) begin
axi_awaddr_r <= s00_axi_awaddr;
end
if (s00_axi_wvalid) begin
axi_wdata_r <= s00_axi_wdata;
axi_wstrb_r <= s00_axi_wstrb;
end
end
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
axi_wvalid_r <= 0;
axi_awvalid_r <= 0;
end else begin
if (axi_awvalid && axi_wvalid) begin
axi_wvalid_r <= 0;
axi_awvalid_r <= 0;
end else if (axi_awvalid) begin
axi_awvalid_r <= 1;
end else if (axi_wvalid) begin
axi_wvalid_r <= 1;
end
end
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg axi_arready;
reg [31 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
wire slv_reg_rden;
wire slv_reg_wren;
assign s00_axi_awready = 1'b1;
assign s00_axi_wready = 1'b1;
assign s00_axi_bresp = axi_bresp;
assign s00_axi_bvalid = axi_bvalid;
assign s00_axi_arready = axi_arready;
assign s00_axi_rvalid = axi_rvalid;
assign s00_axi_rdata = axi_rdata;
assign s00_axi_rresp = axi_rresp;
assign slv_reg_wren = s00_axi_wvalid && s00_axi_awvalid;
assign s00_axi_bvalid = axi_bvalid;
always @(posedge s00_axi_aclk)
if (~s00_axi_aresetn) begin
axi_bresp <= 0;
axi_bvalid <= 0;
end else if (axi_awvalid && axi_wvalid) begin
axi_bresp <= 0;
axi_bvalid <= 1;
end else begin
axi_bresp <= 0;
axi_bvalid <= 0;
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
if (~s00_axi_aresetn) begin
divsor <= 50000000 / 115200;
send_buf_write <= 0;
end else if (slv_reg_wren) begin
end else if (axi_awvalid && axi_wvalid) begin
send_buf_write <= 0;
if ((s00_axi_awaddr & 4'hf) == 4'h4) begin
send_buf_data <= s00_axi_wdata;
if ((axi_awaddr & 4'hf) == 4'h4) begin
send_buf_data <= axi_wdata[7:0];
send_buf_write <= ~recv_buf_full;
end else if ((s00_axi_awaddr & 4'hf) == 4'hc) begin
divsor <= s00_axi_wdata[15:0];
end else if ((axi_awaddr & 4'hf) == 4'hc) begin
divsor <= axi_wdata[15:0];
end
end else begin
end else begin
send_buf_write <= 0;
end
end
reg axi_arready;
reg [3:0] axi_raddr_r;
reg axi_raddr_valid_r;
reg [31 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
wire axi_raddr_valid = s00_axi_arvalid || axi_raddr_valid_r;
wire [3:0] axi_raddr = s00_axi_arvalid ? s00_axi_araddr : axi_raddr_r;
assign s00_axi_arready = axi_arready;
assign s00_axi_rvalid = axi_rvalid;
assign s00_axi_rdata = axi_rdata;
assign s00_axi_rresp = axi_rresp;
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end else if (slv_reg_wren) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end else if (s00_axi_bready && axi_bvalid) begin
axi_bvalid <= 1'b0;
if ( ~s00_axi_aresetn) begin
axi_arready <= 1'b0;
end if (s00_axi_arvalid) begin
axi_arready <= 1'b1;
axi_raddr_r <= s00_axi_araddr;
end else begin
axi_arready <= 1'b0;
end
end
end
always @( posedge s00_axi_aclk )
begin
if (~s00_axi_aresetn) begin
axi_raddr_valid_r <= 0;
end else begin
if (s00_axi_rready && axi_raddr_valid) begin
axi_raddr_valid_r <= 0;
end else if (s00_axi_arvalid) begin
axi_raddr_valid_r <= 1;
end
end
end
always @( posedge s00_axi_aclk )
begin
if ( s00_axi_aresetn == 1'b0 ) begin
if (~s00_axi_aresetn) begin
axi_rdata <= 0;
axi_rvalid <= 0;
recv_buf_read <= 1'b0;
axi_rresp <= 0;
axi_arready <= 0;
end else if (s00_axi_arvalid) begin
recv_buf_read <= 1'b0;
axi_rvalid <= 0;
axi_arready <= 0;
if ((s00_axi_araddr & 4'hf) == 8) begin /* read state */
axi_rdata <= ctl_state;
axi_rvalid <= 1;
axi_arready <= 1;
end else if ((s00_axi_araddr & 4'hf) == 0) begin/* read recv */
end else if (axi_raddr_valid && ~axi_rvalid) begin
if ((axi_raddr & 4'hf) == 0) begin
axi_rdata <= {recv_buf_empty, 23'b0, recv_buf_q};
recv_buf_read <= ~recv_buf_empty;
axi_rvalid <= 1;
axi_arready <= 1;
end else if ((axi_raddr & 4'hf) == 8) begin
axi_rdata <= ctl_state;
end
axi_rvalid <= 1;
end else if (s00_axi_rready && axi_rvalid) begin
axi_rvalid <= 0;
recv_buf_read <= 0;
end else begin
recv_buf_read <= 0;
axi_rvalid <= 0;
axi_arready <= 0;
end
end
......
examples/hdl4se_riscv/verilog/xilinx/xilinx_top.v 0 → 100644
浏览文件 @ 0ae6b329
module riscv_top
(input [2:0] key,
output [3:0] led,
input nwReset,
input uart_rx,
output uart_tx,
input wClk);
/* axi signals */
wire [31 : 0] m00_axi_awaddr;
wire [2 : 0] m00_axi_awprot;
wire m00_axi_awvalid;
wire m00_axi_awready;
wire [31 : 0] m00_axi_wdata;
wire [3 : 0] m00_axi_wstrb;
wire m00_axi_wvalid;
wire m00_axi_wready;
wire [1 : 0] m00_axi_bresp;
wire m00_axi_bvalid;
wire m00_axi_bready;
wire [31 : 0] m00_axi_araddr;
wire [2 : 0] m00_axi_arprot;
wire m00_axi_arvalid;
wire m00_axi_arready;
wire [31 : 0] m00_axi_rdata;
wire [1 : 0] m00_axi_rresp;
wire m00_axi_rvalid;
wire m00_axi_rready;
wire [31 : 0] s00_axi_awaddr;
wire [2 : 0] s00_axi_awprot;
wire s00_axi_awvalid;
wire s00_axi_awready;
wire [31 : 0] s00_axi_wdata;
wire [3 : 0] s00_axi_wstrb;
wire s00_axi_wvalid;
wire s00_axi_wready;
wire [1 : 0] s00_axi_bresp;
wire s00_axi_bvalid;
wire s00_axi_bready;
wire [31 : 0] s00_axi_araddr;
wire [2 : 0] s00_axi_arprot;
wire s00_axi_arvalid;
wire s00_axi_arready;
wire [31 : 0] s00_axi_rdata;
wire [1 : 0] s00_axi_rresp;
wire s00_axi_rvalid;
wire s00_axi_rready;
wire [31 : 0] s01_axi_awaddr;
wire [2 : 0] s01_axi_awprot;
wire s01_axi_awvalid;
wire s01_axi_awready;
wire [31 : 0] s01_axi_wdata;
wire [3 : 0] s01_axi_wstrb;
wire s01_axi_wvalid;
wire s01_axi_wready;
wire [1 : 0] s01_axi_bresp;
wire s01_axi_bvalid;
wire s01_axi_bready;
wire [31 : 0] s01_axi_araddr;
wire [2 : 0] s01_axi_arprot;
wire s01_axi_arvalid;
wire s01_axi_arready;
wire [31 : 0] s01_axi_rdata;
wire [1 : 0] s01_axi_rresp;
wire s01_axi_rvalid;
wire s01_axi_rready;
riscv_core_with_axi_master risc_core
(
.m00_axi_aclk(wClk),
.m00_axi_aresetn(nwReset),
.m00_axi_awaddr(m00_axi_awaddr),
.m00_axi_awprot(m00_axi_awprot),
.m00_axi_awvalid(m00_axi_awvalid),
.m00_axi_awready(m00_axi_awready),
.m00_axi_wdata(m00_axi_wdata),
.m00_axi_wstrb(m00_axi_wstrb),
.m00_axi_wvalid(m00_axi_wvalid),
.m00_axi_wready(m00_axi_wready),
.m00_axi_bresp(m00_axi_bresp),
.m00_axi_bvalid(m00_axi_bvalid),
.m00_axi_bready(m00_axi_bready),
.m00_axi_araddr(m00_axi_araddr),
.m00_axi_arprot(m00_axi_arprot),
.m00_axi_arvalid(m00_axi_arvalid),
.m00_axi_arready(m00_axi_arready),
.m00_axi_rdata(m00_axi_rdata),
.m00_axi_rresp(m00_axi_rresp),
.m00_axi_rvalid(m00_axi_rvalid),
.m00_axi_rready(m00_axi_rready)
);
led_key led_key_inst
(
.s00_axi_aclk(wClk),
.s00_axi_aresetn(nwReset),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready),
.key(key),
.led(led)
);
hdl4se_uart_ctrl_axi uart_inst(
.s00_axi_aclk(wClk),
.s00_axi_aresetn(nwReset),
.s00_axi_awaddr(s01_axi_awaddr),
.s00_axi_awprot(s01_axi_awprot),
.s00_axi_awvalid(s01_axi_awvalid),
.s00_axi_awready(s01_axi_awready),
.s00_axi_wdata(s01_axi_wdata),
.s00_axi_wstrb(s01_axi_wstrb),
.s00_axi_wvalid(s01_axi_wvalid),
.s00_axi_wready(s01_axi_wready),
.s00_axi_bresp(s01_axi_bresp),
.s00_axi_bvalid(s01_axi_bvalid),
.s00_axi_bready(s01_axi_bready),
.s00_axi_araddr(s01_axi_araddr),
.s00_axi_arprot(s01_axi_arprot),
.s00_axi_arvalid(s01_axi_arvalid),
.s00_axi_arready(s01_axi_arready),
.s00_axi_rdata(s01_axi_rdata),
.s00_axi_rresp(s01_axi_rresp),
.s00_axi_rvalid(s01_axi_rvalid),
.s00_axi_rready(s01_axi_rready),
.uart_tx(uart_tx),
.uart_rx(uart_rx)
);
axi1to2 #(
.M00_ADDR_MASK( 32'hfffff000),
.M00_ADDR_START(32'hf0000000),
.M01_ADDR_MASK( 32'hfffff000),
.M01_ADDR_START(32'hf0001000)
) axibar
(
.axi_aclk(wClk),
.axi_aresetn(nwReset),
.s00_axi_awaddr(m00_axi_awaddr),
.s00_axi_awprot(m00_axi_awprot),
.s00_axi_awvalid(m00_axi_awvalid),
.s00_axi_awready(m00_axi_awready),
.s00_axi_wdata(m00_axi_wdata),
.s00_axi_wstrb(m00_axi_wstrb),
.s00_axi_wvalid(m00_axi_wvalid),
.s00_axi_wready(m00_axi_wready),
.s00_axi_bresp(m00_axi_bresp),
.s00_axi_bvalid(m00_axi_bvalid),
.s00_axi_bready(m00_axi_bready),
.s00_axi_araddr(m00_axi_araddr),
.s00_axi_arprot(m00_axi_arprot),
.s00_axi_arvalid(m00_axi_arvalid),
.s00_axi_arready(m00_axi_arready),
.s00_axi_rdata(m00_axi_rdata),
.s00_axi_rresp(m00_axi_rresp),
.s00_axi_rvalid(m00_axi_rvalid),
.s00_axi_rready(m00_axi_rready),
.m00_axi_awaddr(s00_axi_awaddr),
.m00_axi_awprot(s00_axi_awprot),
.m00_axi_awvalid(s00_axi_awvalid),
.m00_axi_awready(s00_axi_awready),
.m00_axi_wdata(s00_axi_wdata),
.m00_axi_wstrb(s00_axi_wstrb),
.m00_axi_wvalid(s00_axi_wvalid),
.m00_axi_wready(s00_axi_wready),
.m00_axi_bresp(s00_axi_bresp),
.m00_axi_bvalid(s00_axi_bvalid),
.m00_axi_bready(s00_axi_bready),
.m00_axi_araddr(s00_axi_araddr),
.m00_axi_arprot(s00_axi_arprot),
.m00_axi_arvalid(s00_axi_arvalid),
.m00_axi_arready(s00_axi_arready),
.m00_axi_rdata(s00_axi_rdata),
.m00_axi_rresp(s00_axi_rresp),
.m00_axi_rvalid(s00_axi_rvalid),
.m00_axi_rready(s00_axi_rready),
.m01_axi_awaddr(s01_axi_awaddr),
.m01_axi_awprot(s01_axi_awprot),
.m01_axi_awvalid(s01_axi_awvalid),
.m01_axi_awready(s01_axi_awready),
.m01_axi_wdata(s01_axi_wdata),
.m01_axi_wstrb(s01_axi_wstrb),
.m01_axi_wvalid(s01_axi_wvalid),
.m01_axi_wready(s01_axi_wready),
.m01_axi_bresp(s01_axi_bresp),
.m01_axi_bvalid(s01_axi_bvalid),
.m01_axi_bready(s01_axi_bready),
.m01_axi_araddr(s01_axi_araddr),
.m01_axi_arprot(s01_axi_arprot),
.m01_axi_arvalid(s01_axi_arvalid),
.m01_axi_arready(s01_axi_arready),
.m01_axi_rdata(s01_axi_rdata),
.m01_axi_rresp(s01_axi_rresp),
.m01_axi_rvalid(s01_axi_rvalid),
.m01_axi_rready(s01_axi_rready)
);
endmodule
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/constrs_1/new/riscv-1.xdc
浏览文件 @ 0ae6b329
......@@ -20,3 +20,5 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports nwReset]
create_clock -period 20.000 -name wClk -waveform {0.000 10.000} [get_ports wClk]
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/design_1.bxml
浏览文件 @ 0ae6b329
......@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="36">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1631782876"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1631782876"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1631782876"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1631782876"/>
<Generation Name="SYNTHESIS" State="STALE" Timestamp="1631838574"/>
<Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1631838574"/>
<Generation Name="SIMULATION" State="STALE" Timestamp="1631838574"/>
<Generation Name="HW_HANDOFF" State="STALE" Timestamp="1631838574"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth\design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
......@@ -42,22 +42,14 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip\design_1_xbar_0\design_1_xbar_0.xci" Type="IP">
<Instance HierarchyPath="riscv_core_with_axi_0_axi_periph/xbar"/>
<File Name="ip\design_1_axi1to2_0_0\design_1_axi1to2_0_0.xci" Type="IP">
<Instance HierarchyPath="axi1to2_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip\design_1_riscv_core_with_axi_0_axi_periph_0\design_1_riscv_core_with_axi_0_axi_periph_0.xci" Type="IP">
<Instance HierarchyPath="riscv_core_with_axi_0_axi_periph"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="design_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
浏览文件 @ 0ae6b329
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
//Date : Thu Sep 16 17:01:15 2021
//Date : Fri Sep 17 08:02:46 2021
//Host : RG6MXLMTA6KAGXI running 64-bit Service Pack 1 (build 7601)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
浏览文件 @ 0ae6b329
......@@ -40,7 +40,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# The design that will be created by this Tcl script contains the following
# module references:
# hdl4se_uart_ctrl_axi, led_key, riscv_core_with_axi_master
# axi1to2, hdl4se_uart_ctrl_axi, led_key, riscv_core_with_axi_master
# Please add the sources of those modules before sourcing this Tcl script.
......@@ -174,6 +174,17 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {50000000} \
] $wClk
# Create instance: axi1to2_0, and set properties
set block_name axi1to2
set block_cell_name axi1to2_0
if { [catch {set axi1to2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $axi1to2_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: hdl4se_uart_ctrl_axi_0, and set properties
set block_name hdl4se_uart_ctrl_axi
set block_cell_name hdl4se_uart_ctrl_axi_0
......@@ -207,28 +218,37 @@ proc create_root_design { parentCell } {
return 1
}
# Create instance: riscv_core_with_axi_0_axi_periph, and set properties
set riscv_core_with_axi_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 riscv_core_with_axi_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {2} \
] $riscv_core_with_axi_0_axi_periph
# Create interface connections
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M00_AXI [get_bd_intf_pins led_key_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M01_AXI [get_bd_intf_pins hdl4se_uart_ctrl_axi_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_m00_axi [get_bd_intf_pins riscv_core_with_axi_0/m00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net axi1to2_0_m00_axi [get_bd_intf_pins axi1to2_0/m00_axi] [get_bd_intf_pins led_key_0/s00_axi]
connect_bd_intf_net -intf_net axi1to2_0_m01_axi [get_bd_intf_pins axi1to2_0/m01_axi] [get_bd_intf_pins hdl4se_uart_ctrl_axi_0/s00_axi]
connect_bd_intf_net -intf_net riscv_core_with_axi_0_m00_axi [get_bd_intf_pins axi1to2_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0/m00_axi]
# Create port connections
connect_bd_net -net hdl4se_uart_ctrl_axi_0_uart_tx [get_bd_ports uart_tx] [get_bd_pins hdl4se_uart_ctrl_axi_0/uart_tx]
connect_bd_net -net key_1 [get_bd_ports key] [get_bd_pins led_key_0/key]
connect_bd_net -net led_key_0_led [get_bd_ports led] [get_bd_pins led_key_0/led]
connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_ports nwReset] [get_bd_pins hdl4se_uart_ctrl_axi_0/s00_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0_axi_periph/ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ARESETN]
connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_ports nwReset] [get_bd_pins axi1to2_0/axi_aresetn] [get_bd_pins hdl4se_uart_ctrl_axi_0/s00_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn]
connect_bd_net -net uart_rx_1 [get_bd_ports uart_rx] [get_bd_pins hdl4se_uart_ctrl_axi_0/uart_rx]
connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins hdl4se_uart_ctrl_axi_0/s00_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk] [get_bd_pins riscv_core_with_axi_0_axi_periph/ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ACLK]
connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins axi1to2_0/axi_aclk] [get_bd_pins hdl4se_uart_ctrl_axi_0/s00_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk]
# Create address segments
# Exclude Address Segments
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces axi1to2_0/m00_axi] [get_bd_addr_segs led_key_0/s00_axi/reg0] SEG_led_key_0_reg0
exclude_bd_addr_seg [get_bd_addr_segs axi1to2_0/m00_axi/SEG_led_key_0_reg0]
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces axi1to2_0/m01_axi] [get_bd_addr_segs hdl4se_uart_ctrl_axi_0/s00_axi/reg0] SEG_hdl4se_uart_ctrl_axi_0_reg0
exclude_bd_addr_seg [get_bd_addr_segs axi1to2_0/m01_axi/SEG_hdl4se_uart_ctrl_axi_0_reg0]
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs axi1to2_0/s00_axi/reg0] SEG_axi1to2_0_reg0
exclude_bd_addr_seg [get_bd_addr_segs riscv_core_with_axi_0/m00_axi/SEG_axi1to2_0_reg0]
create_bd_addr_seg -range 0x00001000 -offset 0xF0001000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs hdl4se_uart_ctrl_axi_0/s00_axi/reg0] SEG_hdl4se_uart_ctrl_axi_0_reg0
exclude_bd_addr_seg [get_bd_addr_segs riscv_core_with_axi_0/m00_axi/SEG_hdl4se_uart_ctrl_axi_0_reg0]
create_bd_addr_seg -range 0x00001000 -offset 0xF0000000 [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs led_key_0/s00_axi/reg0] SEG_led_key_0_reg0
exclude_bd_addr_seg [get_bd_addr_segs riscv_core_with_axi_0/m00_axi/SEG_led_key_0_reg0]
# Restore current instance
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_riscv_core_with_axi_0_0/sim/design_1_riscv_core_with_axi_0_0.v → examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_axi1to2_0_0/sim/design_1_axi1to2_0_0.v
浏览文件 @ 0ae6b329
......@@ -47,16 +47,35 @@
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:riscv_core_with_axi_master:1.0
// IP VLNV: xilinx.com:module_ref:axi1to2:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_riscv_core_with_axi_0_0 (
m00_axi_aclk,
m00_axi_aresetn,
module design_1_axi1to2_0_0 (
axi_aclk,
axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready,
m00_axi_awaddr,
m00_axi_awprot,
m00_axi_awvalid,
......@@ -75,15 +94,74 @@ module design_1_riscv_core_with_axi_0_0 (
m00_axi_rdata,
m00_axi_rresp,
m00_axi_rvalid,
m00_axi_rready
m00_axi_rready,
m01_axi_awaddr,
m01_axi_awprot,
m01_axi_awvalid,
m01_axi_awready,
m01_axi_wdata,
m01_axi_wstrb,
m01_axi_wvalid,
m01_axi_wready,
m01_axi_bresp,
m01_axi_bvalid,
m01_axi_bready,
m01_axi_araddr,
m01_axi_arprot,
m01_axi_arvalid,
m01_axi_arready,
m01_axi_rdata,
m01_axi_rresp,
m01_axi_rvalid,
m01_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aclk, ASSOCIATED_BUSIF m00_axi, ASSOCIATED_RESET m00_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_wClk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m00_axi_aclk CLK" *)
input wire m00_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m00_axi_aresetn RST" *)
input wire m00_axi_aresetn;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axi_aclk, ASSOCIATED_BUSIF m00_axi:m01_axi:s00_axi, ASSOCIATED_RESET axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_wClk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axi_aclk CLK" *)
input wire axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 axi_aresetn RST" *)
input wire axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [31 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [31 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_wClk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R\
USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWADDR" *)
output wire [31 : 0] m00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi AWPROT" *)
......@@ -124,10 +202,74 @@ input wire m00_axi_rvalid;
USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m00_axi RREADY" *)
output wire m00_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi AWADDR" *)
output wire [31 : 0] m01_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi AWPROT" *)
output wire [2 : 0] m01_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi AWVALID" *)
output wire m01_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi AWREADY" *)
input wire m01_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi WDATA" *)
output wire [31 : 0] m01_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi WSTRB" *)
output wire [3 : 0] m01_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi WVALID" *)
output wire m01_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi WREADY" *)
input wire m01_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi BRESP" *)
input wire [1 : 0] m01_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi BVALID" *)
input wire m01_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi BREADY" *)
output wire m01_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi ARADDR" *)
output wire [31 : 0] m01_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi ARPROT" *)
output wire [2 : 0] m01_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi ARVALID" *)
output wire m01_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi ARREADY" *)
input wire m01_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi RDATA" *)
input wire [31 : 0] m01_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi RRESP" *)
input wire [1 : 0] m01_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi RVALID" *)
input wire m01_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m01_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_wClk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, R\
USER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m01_axi RREADY" *)
output wire m01_axi_rready;
riscv_core_with_axi_master inst (
.m00_axi_aclk(m00_axi_aclk),
.m00_axi_aresetn(m00_axi_aresetn),
axi1to2 #(
.M00_ADDR_MASK(32'HFFFFF000),
.M00_ADDR_START(32'H00000000),
.M01_ADDR_MASK(32'HFFFFF000),
.M01_ADDR_START(32'H00001000)
) inst (
.axi_aclk(axi_aclk),
.axi_aresetn(axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready),
.m00_axi_awaddr(m00_axi_awaddr),
.m00_axi_awprot(m00_axi_awprot),
.m00_axi_awvalid(m00_axi_awvalid),
......@@ -146,6 +288,25 @@ output wire m00_axi_rready;
.m00_axi_rdata(m00_axi_rdata),
.m00_axi_rresp(m00_axi_rresp),
.m00_axi_rvalid(m00_axi_rvalid),
.m00_axi_rready(m00_axi_rready)
.m00_axi_rready(m00_axi_rready),
.m01_axi_awaddr(m01_axi_awaddr),
.m01_axi_awprot(m01_axi_awprot),
.m01_axi_awvalid(m01_axi_awvalid),
.m01_axi_awready(m01_axi_awready),
.m01_axi_wdata(m01_axi_wdata),
.m01_axi_wstrb(m01_axi_wstrb),
.m01_axi_wvalid(m01_axi_wvalid),
.m01_axi_wready(m01_axi_wready),
.m01_axi_bresp(m01_axi_bresp),
.m01_axi_bvalid(m01_axi_bvalid),
.m01_axi_bready(m01_axi_bready),
.m01_axi_araddr(m01_axi_araddr),
.m01_axi_arprot(m01_axi_arprot),
.m01_axi_arvalid(m01_axi_arvalid),
.m01_axi_arready(m01_axi_arready),
.m01_axi_rdata(m01_axi_rdata),
.m01_axi_rresp(m01_axi_rresp),
.m01_axi_rvalid(m01_axi_rvalid),
.m01_axi_rready(m01_axi_rready)
);
endmodule
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_hdl4se_uart_ctrl_axi_0_0/design_1_hdl4se_uart_ctrl_axi_0_0.xci
浏览文件 @ 0ae6b329
......@@ -79,7 +79,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -99,7 +99,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_hdl4se_uart_ctrl_axi_0_0/design_1_hdl4se_uart_ctrl_axi_0_0.xml
浏览文件 @ 0ae6b329
......@@ -1099,7 +1099,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -1119,7 +1119,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_led_key_0_0/design_1_led_key_0_0.xci
浏览文件 @ 0ae6b329
......@@ -79,7 +79,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -99,7 +99,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_led_key_0_0/design_1_led_key_0_0.xml
浏览文件 @ 0ae6b329
......@@ -1044,7 +1044,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -1064,7 +1064,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/design_1/ip/design_1_riscv_core_with_axi_0_0/design_1_riscv_core_with_axi_0_0.xci
浏览文件 @ 0ae6b329
......@@ -15,9 +15,9 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.CLK_DOMAIN">design_1_wClk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_CACHE">0</spirit:configurableElementValue>
......@@ -42,8 +42,8 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.CLK_DOMAIN">design_1_wClk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.FREQ_HZ">50000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
......@@ -76,9 +76,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -97,8 +95,6 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M00_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
examples/hdl4se_riscv/z7/test_riscv/test_riscv.srcs/sources_1/bd/mref/riscv_core_with_axi_master/component.xml
浏览文件 @ 0ae6b329
......@@ -637,7 +637,7 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-09-15T10:51:37Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2021-09-17T00:25:36Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
......
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