202108312033

examples/hdl4se_riscv/de2/.gitattributes

+###############################################################################
+# Set default behavior to automatically normalize line endings.
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+* text=auto
+
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+# Note: This is only used by command line
+###############################################################################
+#*.cs     diff=csharp
+
+###############################################################################
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+#
+# Merging from the command prompt will add diff markers to the files if there
+# are conflicts (Merging from VS is not affected by the settings below, in VS
+# the diff markers are never inserted). Diff markers may cause the following 
+# file extensions to fail to load in VS. An alternative would be to treat
+# these files as binary and thus will always conflict and require user
+# intervention with every merge. To do so, just uncomment the entries below
+###############################################################################
+#*.sln       merge=binary
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+
+###############################################################################
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+# Convert binary document formats to text before diffing them. This feature
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examples/hdl4se_riscv/de2/.gitignore

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+[Dd]ebugPS/
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+
+#altera fpga
+db/
+greybox_tmp/
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+# Chutzpah Test files
+_Chutzpah*
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+# Visual C++ cache files
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+
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+# ReSharper is a .NET coding add-in
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+# DotCover is a Code Coverage Tool
+*.dotCover
+
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+
+# Visual Studio code coverage results
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+
+# NCrunch
+_NCrunch_*
+.*crunch*.local.xml
+nCrunchTemp_*
+
+# MightyMoose
+*.mm.*
+AutoTest.Net/
+
+# Web workbench (sass)
+.sass-cache/
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+# Installshield output folder
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+
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+# Publish Web Output
+*.[Pp]ublish.xml
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+# Note: Comment the next line if you want to checkin your web deploy settings,
+# but database connection strings (with potential passwords) will be unencrypted
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+# Microsoft Azure Web App publish settings. Comment the next line if you want to
+# checkin your Azure Web App publish settings, but sensitive information contained
+# in these scripts will be unencrypted
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+*.snupkg
+# The packages folder can be ignored because of Package Restore
+**/[Pp]ackages/*
+# except build/, which is used as an MSBuild target.
+!**/[Pp]ackages/build/
+# Uncomment if necessary however generally it will be regenerated when needed
+#!**/[Pp]ackages/repositories.config
+# NuGet v3's project.json files produces more ignorable files
+*.nuget.props
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+# Microsoft Azure Build Output
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+
+# Windows Store app package directories and files
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+# Including strong name files can present a security risk
+# (https://github.com/github/gitignore/pull/2483#issue-259490424)
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+# (https://github.com/github/gitignore/pull/1529#issuecomment-104372622)
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+# Backup & report files from converting an old project file
+# to a newer Visual Studio version. Backup files are not needed,
+# because we have git ;-)
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+*- [Bb]ackup.rdl
+*- [Bb]ackup ([0-9]).rdl
+*- [Bb]ackup ([0-9][0-9]).rdl
+
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+FakesAssemblies/
+
+# GhostDoc plugin setting file
+*.GhostDoc.xml
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+
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+
+# Paket dependency manager
+.paket/paket.exe
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+.fake/
+
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+.cr/personal
+
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+__pycache__/
+*.pyc
+
+# Cake - Uncomment if you are using it
+# tools/**
+# !tools/packages.config
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+# Tabs Studio
+*.tss
+
+# Telerik's JustMock configuration file
+*.jmconfig
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+*.btp.cs
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+*.xsd.cs
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+OpenCover/
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+ASALocalRun/
+
+# MSBuild Binary and Structured Log
+*.binlog
+
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+*.nvuser
+
+# MFractors (Xamarin productivity tool) working folder
+.mfractor/
+
+# Local History for Visual Studio
+.localhistory/
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+# BeatPulse healthcheck temp database
+healthchecksdb
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+# Backup folder for Package Reference Convert tool in Visual Studio 2017
+MigrationBackup/
+
+# Ionide (cross platform F# VS Code tools) working folder
+.ionide/
+
+# Fody - auto-generated XML schema
+FodyWeavers.xsd
\ No newline at end of file

examples/hdl4se_riscv/de2/de2_riscv_v3.qpf

+DATE = "20:10:06 August 31, 2021"
+QUARTUS_VERSION = "12.0"
+
+# Revisions
+
+PROJECT_REVISION = "de2_riscv_v3"

examples/hdl4se_riscv/de2/de2_riscv_v3.sdc

+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

examples/hdl4se_riscv/de2/de2_riscv_v3.v

+
+//=======================================================
+//  This code is generated by Terasic System Builder
+//=======================================================
+
+`define USECLOCK50
+module de2_riscv_v3(
+
+	//////////// CLOCK //////////
+	CLOCK_50,
+	CLOCK2_50,
+	CLOCK3_50,
+
+	//////////// Sma //////////
+	SMA_CLKIN,
+	SMA_CLKOUT,
+
+	//////////// LED //////////
+	LEDG,
+	LEDR,
+
+	//////////// KEY //////////
+	KEY,
+
+	//////////// EX_IO //////////
+	EX_IO,
+
+	//////////// SW //////////
+	SW,
+
+	//////////// SEG7 //////////
+	HEX0,
+	HEX1,
+	HEX2,
+	HEX3,
+	HEX4,
+	HEX5,
+	HEX6,
+	HEX7,
+
+	//////////// LCD //////////
+	LCD_BLON,
+	LCD_DATA,
+	LCD_EN,
+	LCD_ON,
+	LCD_RS,
+	LCD_RW,
+
+	//////////// RS232 //////////
+	UART_CTS,
+	UART_RTS,
+	UART_RXD,
+	UART_TXD,
+
+	//////////// PS2 for Keyboard and Mouse //////////
+	PS2_CLK,
+	PS2_CLK2,
+	PS2_DAT,
+	PS2_DAT2,
+
+	//////////// SDCARD //////////
+	SD_CLK,
+	SD_CMD,
+	SD_DAT,
+	SD_WP_N,
+
+	//////////// VGA //////////
+	VGA_B,
+	VGA_BLANK_N,
+	VGA_CLK,
+	VGA_G,
+	VGA_HS,
+	VGA_R,
+	VGA_SYNC_N,
+	VGA_VS,
+
+	//////////// Audio //////////
+	AUD_ADCDAT,
+	AUD_ADCLRCK,
+	AUD_BCLK,
+	AUD_DACDAT,
+	AUD_DACLRCK,
+	AUD_XCK,
+
+	//////////// I2C for EEPROM //////////
+	EEP_I2C_SCLK,
+	EEP_I2C_SDAT,
+
+	//////////// I2C for Audio Tv-Decoder  //////////
+	I2C_SCLK,
+	I2C_SDAT,
+
+	//////////// Ethernet 0 //////////
+	ENET0_GTX_CLK,
+	ENET0_INT_N,
+	ENET0_LINK100,
+	ENET0_MDC,
+	ENET0_MDIO,
+	ENET0_RST_N,
+	ENET0_RX_CLK,
+	ENET0_RX_COL,
+	ENET0_RX_CRS,
+	ENET0_RX_DATA,
+	ENET0_RX_DV,
+	ENET0_RX_ER,
+	ENET0_TX_CLK,
+	ENET0_TX_DATA,
+	ENET0_TX_EN,
+	ENET0_TX_ER,
+	ENETCLK_25,
+
+	//////////// Ethernet 1 //////////
+	ENET1_GTX_CLK,
+	ENET1_INT_N,
+	ENET1_LINK100,
+	ENET1_MDC,
+	ENET1_MDIO,
+	ENET1_RST_N,
+	ENET1_RX_CLK,
+	ENET1_RX_COL,
+	ENET1_RX_CRS,
+	ENET1_RX_DATA,
+	ENET1_RX_DV,
+	ENET1_RX_ER,
+	ENET1_TX_CLK,
+	ENET1_TX_DATA,
+	ENET1_TX_EN,
+	ENET1_TX_ER,
+
+	//////////// TV Decoder //////////
+	TD_CLK27,
+	TD_DATA,
+	TD_HS,
+	TD_RESET_N,
+	TD_VS,
+
+	//////////// USB 2.0 OTG (Cypress CY7C67200) //////////
+	OTG_ADDR,
+	OTG_CS_N,
+	OTG_DATA,
+	OTG_INT,
+	OTG_RD_N,
+	OTG_RST_N,
+	OTG_WE_N,
+
+	//////////// IR Receiver //////////
+	IRDA_RXD,
+
+	//////////// SDRAM //////////
+	DRAM_ADDR,
+	DRAM_BA,
+	DRAM_CAS_N,
+	DRAM_CKE,
+	DRAM_CLK,
+	DRAM_CS_N,
+	DRAM_DQ,
+	DRAM_DQM,
+	DRAM_RAS_N,
+	DRAM_WE_N,
+
+	//////////// SRAM //////////
+	SRAM_ADDR,
+	SRAM_CE_N,
+	SRAM_DQ,
+	SRAM_LB_N,
+	SRAM_OE_N,
+	SRAM_UB_N,
+	SRAM_WE_N,
+
+	//////////// Flash //////////
+	FL_ADDR,
+	FL_CE_N,
+	FL_DQ,
+	FL_OE_N,
+	FL_RST_N,
+	FL_RY,
+	FL_WE_N,
+	FL_WP_N,
+
+	//////////// GPIO, GPIO connect to GPIO Default //////////
+	GPIO 
+);
+
+//=======================================================
+//  PARAMETER declarations
+//=======================================================
+
+
+//=======================================================
+//  PORT declarations
+//=======================================================
+
+//////////// CLOCK //////////
+input 		          		CLOCK_50;
+input 		          		CLOCK2_50;
+input 		          		CLOCK3_50;
+
+//////////// Sma //////////
+input 		          		SMA_CLKIN;
+output		          		SMA_CLKOUT;
+
+//////////// LED //////////
+output		     [8:0]		LEDG;
+output		    [17:0]		LEDR;
+
+//////////// KEY //////////
+input 		     [3:0]		KEY;
+
+//////////// EX_IO //////////
+inout 		     [6:0]		EX_IO;
+
+//////////// SW //////////
+input 		    [17:0]		SW;
+
+//////////// SEG7 //////////
+output		     [6:0]		HEX0;
+output		     [6:0]		HEX1;
+output		     [6:0]		HEX2;
+output		     [6:0]		HEX3;
+output		     [6:0]		HEX4;
+output		     [6:0]		HEX5;
+output		     [6:0]		HEX6;
+output		     [6:0]		HEX7;
+
+//////////// LCD //////////
+output		          		LCD_BLON;
+inout 		     [7:0]		LCD_DATA;
+output		          		LCD_EN;
+output		          		LCD_ON;
+output		          		LCD_RS;
+output		          		LCD_RW;
+
+//////////// RS232 //////////
+input 		          		UART_CTS;
+output		          		UART_RTS;
+input 		          		UART_RXD;
+output		          		UART_TXD;
+
+//////////// PS2 for Keyboard and Mouse //////////
+inout 		          		PS2_CLK;
+inout 		          		PS2_CLK2;
+inout 		          		PS2_DAT;
+inout 		          		PS2_DAT2;
+
+//////////// SDCARD //////////
+output		          		SD_CLK;
+inout 		          		SD_CMD;
+inout 		     [3:0]		SD_DAT;
+input 		          		SD_WP_N;
+
+//////////// VGA //////////
+output		     [7:0]		VGA_B;
+output		          		VGA_BLANK_N;
+output		          		VGA_CLK;
+output		     [7:0]		VGA_G;
+output		          		VGA_HS;
+output		     [7:0]		VGA_R;
+output		          		VGA_SYNC_N;
+output		          		VGA_VS;
+
+//////////// Audio //////////
+input 		          		AUD_ADCDAT;
+inout 		          		AUD_ADCLRCK;
+inout 		          		AUD_BCLK;
+output		          		AUD_DACDAT;
+inout 		          		AUD_DACLRCK;
+output		          		AUD_XCK;
+
+//////////// I2C for EEPROM //////////
+output		          		EEP_I2C_SCLK;
+inout 		          		EEP_I2C_SDAT;
+
+//////////// I2C for Audio Tv-Decoder  //////////
+output		          		I2C_SCLK;
+inout 		          		I2C_SDAT;
+
+//////////// Ethernet 0 //////////
+output		          		ENET0_GTX_CLK;
+input 		          		ENET0_INT_N;
+input 		          		ENET0_LINK100;
+output		          		ENET0_MDC;
+inout 		          		ENET0_MDIO;
+output		          		ENET0_RST_N;
+input 		          		ENET0_RX_CLK;
+input 		          		ENET0_RX_COL;
+input 		          		ENET0_RX_CRS;
+input 		     [3:0]		ENET0_RX_DATA;
+input 		          		ENET0_RX_DV;
+input 		          		ENET0_RX_ER;
+input 		          		ENET0_TX_CLK;
+output		     [3:0]		ENET0_TX_DATA;
+output		          		ENET0_TX_EN;
+output		          		ENET0_TX_ER;
+input 		          		ENETCLK_25;
+
+//////////// Ethernet 1 //////////
+output		          		ENET1_GTX_CLK;
+input 		          		ENET1_INT_N;
+input 		          		ENET1_LINK100;
+output		          		ENET1_MDC;
+inout 		          		ENET1_MDIO;
+output		          		ENET1_RST_N;
+input 		          		ENET1_RX_CLK;
+input 		          		ENET1_RX_COL;
+input 		          		ENET1_RX_CRS;
+input 		     [3:0]		ENET1_RX_DATA;
+input 		          		ENET1_RX_DV;
+input 		          		ENET1_RX_ER;
+input 		          		ENET1_TX_CLK;
+output		     [3:0]		ENET1_TX_DATA;
+output		          		ENET1_TX_EN;
+output		          		ENET1_TX_ER;
+
+//////////// TV Decoder //////////
+input 		          		TD_CLK27;
+input 		     [7:0]		TD_DATA;
+input 		          		TD_HS;
+output		          		TD_RESET_N;
+input 		          		TD_VS;
+
+//////////// USB 2.0 OTG (Cypress CY7C67200) //////////
+output		     [1:0]		OTG_ADDR;
+output		          		OTG_CS_N;
+inout 		    [15:0]		OTG_DATA;
+input 		          		OTG_INT;
+output		          		OTG_RD_N;
+output		          		OTG_RST_N;
+output		          		OTG_WE_N;
+
+//////////// IR Receiver //////////
+input 		          		IRDA_RXD;
+
+//////////// SDRAM //////////
+output		    [12:0]		DRAM_ADDR;
+output		     [1:0]		DRAM_BA;
+output		          		DRAM_CAS_N;
+output		          		DRAM_CKE;
+output		          		DRAM_CLK;
+output		          		DRAM_CS_N;
+inout 		    [31:0]		DRAM_DQ;
+output		     [3:0]		DRAM_DQM;
+output		          		DRAM_RAS_N;
+output		          		DRAM_WE_N;
+
+//////////// SRAM //////////
+output		    [19:0]		SRAM_ADDR;
+output		          		SRAM_CE_N;
+inout 		    [15:0]		SRAM_DQ;
+output		          		SRAM_LB_N;
+output		          		SRAM_OE_N;
+output		          		SRAM_UB_N;
+output		          		SRAM_WE_N;
+
+//////////// Flash //////////
+output		    [22:0]		FL_ADDR;
+output		          		FL_CE_N;
+inout 		     [7:0]		FL_DQ;
+output		          		FL_OE_N;
+output		          		FL_RST_N;
+input 		          		FL_RY;
+output		          		FL_WE_N;
+output		          		FL_WP_N;
+
+//////////// GPIO, GPIO connect to GPIO Default //////////
+inout 		    [35:0]		GPIO;
+
+
+  wire        uart_tx;
+  wire        uart_rx;
+  assign GPIO[5] = uart_tx;
+  assign GPIO[7] = 1'bz;
+  assign      uart_rx = GPIO[7];
+
+  assign LEDR[0] = uart_tx;
+  assign LEDR[1] = uart_rx;
+
+`ifdef USECLOCK50
+	wire wClk = CLOCK_50;
+`else
+	wire clk100MHz, clk75MHz, clklocked;
+	clk100M clk100(.refclk(CLOCK_50),
+	               .rst(~KEY[3]),
+				   .outclk_0(clk100MHz), 
+				   .outclk_1(clk75MHz),
+				   .locked(clklocked));
+				   
+	wire wClk = clk100MHz;
+`endif
+	wire nwReset = KEY[3];
+
+    wire wWrite, wRead;
+    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
+    wire [3:0]  bWriteMask;
+
+	assign bReadDataKey = {18'b0, KEY, SW};
+
+	reg readcmd;
+	reg [31:0] readaddr;
+
+	always @(posedge wClk) begin
+		if (!nwReset) begin
+			readcmd <= 1'b0;
+			readaddr <= 32'b0;
+		end else begin
+			readcmd <= wRead;
+			readaddr <= bReadAddr;
+		end
+	end
+    
+    assign bReadData = 
+            ((readaddr & 32'hffffff00) == 32'hF0000000) ? bReadDataKey : (
+            ((readaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : (
+            ((readaddr & 32'hffffff00) == 32'hF0000100) ? bReadDataUart : (32'hffffffff)
+			)
+            );
+
+    wire [29:0] ramaddr;
+    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];
+
+    wire [4:0]  regno;
+    wire [3:0]  regena;
+    wire [31:0] regwrdata;
+    wire        regwren;
+    wire [31:0] regrddata;
+    wire [4:0]  regno2;
+    wire [3:0]  regena2;
+    wire [31:0] regwrdata2;
+    wire        regwren2;
+    wire [31:0] regrddata2;
+
+	uart_ctrl uart_ctrl(
+		.wClk(wClk), 
+		.nwReset(nwReset),
+		.wRead(((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0), 
+		.bReadAddr(bReadAddr),
+		.wWrite(((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0), 
+		.bWriteAddr(bWriteAddr),
+		.bWriteData(bWriteData),
+		.bReadData(bReadDataUart),
+		.uart_tx(uart_tx), 
+		.uart_rx(uart_rx),
+		.dataready(LEDR[2]),
+		.sendready(LEDR[3]),
+		.sendfull(LEDR[4]),
+		.recvempty(LEDR[5])
+	);
+
+	reg [4:0] lastregno;
+	reg [4:0] lastregno2;
+
+	always @(posedge wClk) begin
+		lastregno <= regno;
+		lastregno2 <= regno2;
+	end
+
+    regfile    regs(regno, regena, wClk, regwrdata, regwren, regrddata);
+    regfile    regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
+    ram128kB    ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam);
+	riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
+                regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata,
+				regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2
+				);
+
+
+
+//=======================================================
+//  Structural coding
+//=======================================================
+
+
+    reg [6:0] led0;
+	reg [6:0] led1;
+	reg [6:0] led2;
+	reg [6:0] led3;
+	reg [6:0] led4;
+	reg [6:0] led5;
+	reg [6:0] led6;
+	reg [6:0] led7;
+	assign HEX0 = ~led0;
+	assign HEX1 = ~led1;
+	assign HEX2 = ~led2;
+	assign HEX3 = ~led3;
+	assign HEX4 = ~led4;
+	assign HEX5 = ~led5;
+	assign HEX6 = ~led6;
+	assign HEX7 = ~led7;
+
+	
+
+	always @(posedge wClk) begin
+		if (!nwReset) begin
+			led0 <= 8'h3f;
+			led1 <= 8'h3f;
+			led2 <= 8'h3f;
+			led3 <= 8'h3f;
+			led4 <= 8'h3f;
+			led5 <= 8'h3f;
+		end else begin
+			if (SW[17]) begin
+				led0 <= 8'h06;
+				led1 <= 8'h06;
+				led2 <= 8'h06;
+				led3 <= 8'h07;
+				led4 <= 8'h07;
+				led5 <= 8'h07;				
+			end
+			else if (SW[16]) begin
+				led0 <= 8'h3f;
+				led1 <= 8'h06;
+				led2 <= 8'h5b;
+				led3 <= 8'h4f;
+				led4 <= 8'h66;
+				led5 <= 8'h6d;				
+			end
+			else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin
+				if (bWriteAddr[7:0] == 8'h10) begin
+					led0 <= bWriteData[6:0];
+					led1 <= bWriteData[14:8];
+					led2 <= bWriteData[22:16];
+					led3 <= bWriteData[30:24];
+				end else if (bWriteAddr[7:0] == 8'h14) begin
+					led4 <= bWriteData[6:0];
+					led5 <= bWriteData[14:8];
+				end
+			end
+		end
+	end
+
+endmodule

examples/hdl4se_riscv/test_code/test.info

@@ -10,7 +10,7 @@ ELF Header:
   Version:                           0x1
   Entry point address:               0x8c
   Start of program headers:          52 (bytes into file)
-  Start of section headers:          16592 (bytes into file)
+  Start of section headers:          16588 (bytes into file)
   Flags:                             0x0
   Size of this header:               52 (bytes)
   Size of program headers:           32 (bytes)
@@ -31,18 +31,18 @@ Section Headers:
   [ 7] .sdata            PROGBITS        00002728 001728 00000c 00  WA  0   0  4
   [ 8] .bss              NOBITS          00002734 001734 00001c 00  WA  0   0  4
   [ 9] .comment          PROGBITS        00000000 001734 000012 01  MS  0   0  1
-  [10] .riscv.attributes RISCV_ATTRIBUTE 00000000 001746 000026 00      0   0  1
-  [11] .debug_aranges    PROGBITS        00000000 00176c 000038 00      0   0  1
-  [12] .debug_info       PROGBITS        00000000 0017a4 000839 00      0   0  1
-  [13] .debug_abbrev     PROGBITS        00000000 001fdd 000216 00      0   0  1
-  [14] .debug_line       PROGBITS        00000000 0021f3 000766 00      0   0  1
-  [15] .debug_str        PROGBITS        00000000 002959 00029a 01  MS  0   0  1
-  [16] .debug_line_str   PROGBITS        00000000 002bf3 0000aa 01  MS  0   0  1
-  [17] .debug_loclists   PROGBITS        00000000 002c9d 000a99 00      0   0  1
-  [18] .debug_rnglists   PROGBITS        00000000 003736 000111 00      0   0  1
-  [19] .symtab           SYMTAB          00000000 003848 0004f0 10     20  50  4
-  [20] .strtab           STRTAB          00000000 003d38 0002b0 00      0   0  1
-  [21] .shstrtab         STRTAB          00000000 003fe8 0000e8 00      0   0  1
+  [10] .riscv.attributes RISCV_ATTRIBUTE 00000000 001746 000021 00      0   0  1
+  [11] .debug_aranges    PROGBITS        00000000 001767 000038 00      0   0  1
+  [12] .debug_info       PROGBITS        00000000 00179f 000839 00      0   0  1
+  [13] .debug_abbrev     PROGBITS        00000000 001fd8 000216 00      0   0  1
+  [14] .debug_line       PROGBITS        00000000 0021ee 000766 00      0   0  1
+  [15] .debug_str        PROGBITS        00000000 002954 000296 01  MS  0   0  1
+  [16] .debug_line_str   PROGBITS        00000000 002bea 0000b0 01  MS  0   0  1
+  [17] .debug_loclists   PROGBITS        00000000 002c9a 000a99 00      0   0  1
+  [18] .debug_rnglists   PROGBITS        00000000 003733 000111 00      0   0  1
+  [19] .symtab           SYMTAB          00000000 003844 0004f0 10     20  50  4
+  [20] .strtab           STRTAB          00000000 003d34 0002b0 00      0   0  1
+  [21] .shstrtab         STRTAB          00000000 003fe4 0000e8 00      0   0  1
 Key to Flags:
   W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
   L (link order), O (extra OS processing required), G (group), T (TLS),
@@ -153,4 +153,4 @@ No version information found in this file.
 Attribute Section: riscv
 File Attributes
   Tag_RISCV_stack_align: 16-bytes
-  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0"
+  Tag_RISCV_arch: "rv32i2p0_m2p0"