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809d9d8b
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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
809d9d8b
编写于
8月 30, 2021
作者:
饶先宏
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电子邮件补丁
差异文件
202108301847
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ad1c8f30
变更
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展开全部
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Showing
39 changed file
with
72437 addition
and
9486 deletion
+72437
-9486
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
+9
-9
examples/hdl4se_riscv/de1/de1_riscv.done
examples/hdl4se_riscv/de1/de1_riscv.done
+1
-1
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
+1814
-1764
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
+5
-5
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
+23
-17
examples/hdl4se_riscv/de1/de1_riscv.jdi
examples/hdl4se_riscv/de1/de1_riscv.jdi
+1
-1
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
+1044
-852
examples/hdl4se_riscv/de1/de1_riscv.map.summary
examples/hdl4se_riscv/de1/de1_riscv.map.summary
+4
-4
examples/hdl4se_riscv/de1/de1_riscv.qsf
examples/hdl4se_riscv/de1/de1_riscv.qsf
+2
-0
examples/hdl4se_riscv/de1/de1_riscv.sof
examples/hdl4se_riscv/de1/de1_riscv.sof
+0
-0
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
+1546
-1381
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
+52
-20
examples/hdl4se_riscv/de1/de1_riscv_v3.v
examples/hdl4se_riscv/de1/de1_riscv_v3.v
+5
-5
examples/hdl4se_riscv/de1/ram/ram128kB.qip
examples/hdl4se_riscv/de1/ram/ram128kB.qip
+4
-0
examples/hdl4se_riscv/de1/ram/ram128kB.v
examples/hdl4se_riscv/de1/ram/ram128kB.v
+181
-0
examples/hdl4se_riscv/de1/ram/ram128kB_bb.v
examples/hdl4se_riscv/de1/ram/ram128kB_bb.v
+130
-0
examples/hdl4se_riscv/de1/ram/ram16kB.qip
examples/hdl4se_riscv/de1/ram/ram16kB.qip
+4
-0
examples/hdl4se_riscv/de1/ram/ram16kB.v
examples/hdl4se_riscv/de1/ram/ram16kB.v
+181
-0
examples/hdl4se_riscv/de1/ram/ram16kB_bb.v
examples/hdl4se_riscv/de1/ram/ram16kB_bb.v
+130
-0
examples/hdl4se_riscv/de1/ram128kB.qip
examples/hdl4se_riscv/de1/ram128kB.qip
+0
-0
examples/hdl4se_riscv/de1/ram16kB.qip
examples/hdl4se_riscv/de1/ram16kB.qip
+0
-0
examples/hdl4se_riscv/de1/test.mif
examples/hdl4se_riscv/de1/test.mif
+31976
-1256
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
+5
-5
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv.h
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv.h
+1
-1
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v3.c
...ples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v3.c
+10
-4
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
+12
-20
examples/hdl4se_riscv/hdl4se_riscv_sim/main_v2.c
examples/hdl4se_riscv/hdl4se_riscv_sim/main_v2.c
+1
-0
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v3.c
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v3.c
+12
-5
examples/hdl4se_riscv/test_code/main_v2.c
examples/hdl4se_riscv/test_code/main_v2.c
+74
-31
examples/hdl4se_riscv/test_code/test.cod
examples/hdl4se_riscv/test_code/test.cod
+285
-226
examples/hdl4se_riscv/test_code/test.elf
examples/hdl4se_riscv/test_code/test.elf
+0
-0
examples/hdl4se_riscv/test_code/test.hex
examples/hdl4se_riscv/test_code/test.hex
+365
-305
examples/hdl4se_riscv/test_code/test.info
examples/hdl4se_riscv/test_code/test.info
+105
-104
examples/hdl4se_riscv/test_code/test.mif
examples/hdl4se_riscv/test_code/test.mif
+31976
-1256
examples/hdl4se_riscv/test_code/test.sh
examples/hdl4se_riscv/test_code/test.sh
+1
-1
examples/hdl4se_riscv/test_code/test.txt
examples/hdl4se_riscv/test_code/test.txt
+2367
-2128
examples/hdl4se_riscv/verilog/riscv_core_v3.v
examples/hdl4se_riscv/verilog/riscv_core_v3.v
+5
-5
examples/hdl4se_riscv/verilog/riscv_sim_dump_v3.v
examples/hdl4se_riscv/verilog/riscv_sim_dump_v3.v
+101
-75
examples/hdl4se_riscv/verilog/riscv_sim_v3.v
examples/hdl4se_riscv/verilog/riscv_sim_v3.v
+5
-5
未找到文件。
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
浏览文件 @
809d9d8b
Assembler report for de1_riscv
Sun Aug 29 18:52:14
2021
Mon Aug 30 18:42:51
2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...
...
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful -
Sun Aug 29 18:52:14
2021 ;
; Assembler Status ; Successful -
Mon Aug 30 18:42:50
2021 ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
...
...
@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ;
; JTAG usercode ; 0x0
1326DBA
;
; Checksum ; 0x0
1326DBA
;
; JTAG usercode ; 0x0
2745756
;
; Checksum ; 0x0
2745756
;
+----------------+--------------------------------------------------------------------+
...
...
@@ -103,13 +103,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started:
Sun Aug 29 18:52:05
2021
Info: Processing started:
Mon Aug 30 18:42:31
2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory:
480
3 megabytes
Info: Processing ended:
Sun Aug 29 18:52:14
2021
Info: Elapsed time: 00:00:
09
Info: Total CPU time (on all processors): 00:00:
0
9
Info: Peak virtual memory:
67
3 megabytes
Info: Processing ended:
Mon Aug 30 18:42:51
2021
Info: Elapsed time: 00:00:
20
Info: Total CPU time (on all processors): 00:00:
1
9
examples/hdl4se_riscv/de1/de1_riscv.done
浏览文件 @
809d9d8b
Sun Aug 29 18:52:30
2021
Mon Aug 30 18:43:39
2021
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
浏览文件 @
809d9d8b
Fitter Status : Successful -
Sun Aug 29 18:52:02
2021
Fitter Status : Successful -
Mon Aug 30 18:42:25
2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Preliminary
Logic utilization (in ALMs) : 2,
653 / 32,070 ( 8
% )
Total registers :
2042
Logic utilization (in ALMs) : 2,
789 / 32,070 ( 9
% )
Total registers :
1998
Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0
Total block memory bits :
82,944 / 4,065,280 ( 2
% )
Total block memory bits :
1,067,008 / 4,065,280 ( 26
% )
Total DSP Blocks : 10 / 87 ( 11 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0
Total PLLs :
0 / 6 ( 0
% )
Total PLLs :
1 / 6 ( 17
% )
Total DLLs : 0 / 4 ( 0 % )
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
浏览文件 @
809d9d8b
Flow report for de1_riscv
Sun Aug 29 18:52:29
2021
Mon Aug 30 18:43:38
2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...
...
@@ -40,24 +40,24 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+---------------------------------------------+
; Flow Status ; Successful -
Sun Aug 29 18:52:14
2021 ;
; Flow Status ; Successful -
Mon Aug 30 18:42:50
2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ; 2,
653 / 32,070 ( 8
% ) ;
; Total registers ;
2042
;
; Logic utilization (in ALMs) ; 2,
789 / 32,070 ( 9
% ) ;
; Total registers ;
1998
;
; Total pins ; 204 / 457 ( 45 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ;
82,944 / 4,065,280 ( 2 % )
;
; Total block memory bits ;
1,067,008 / 4,065,280 ( 26 % )
;
; Total DSP Blocks ; 10 / 87 ( 11 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total PLLs ;
0 / 6 ( 0 % )
;
; Total PLLs ;
1 / 6 ( 17 % )
;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+---------------------------------------------+
...
...
@@ -67,7 +67,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/
29/2021 18:50:58
;
; Start date & time ; 08/
30/2021 18:39:31
;
; Main task ; Compilation ;
; Revision Name ; de1_riscv ;
+-------------------+---------------------+
...
...
@@ -78,7 +78,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; COMPILER_SIGNATURE_ID ;
101574253398716.163023425830188
; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ;
621136229624.163031997154204
; -- ; -- ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
...
...
@@ -93,6 +93,8 @@ applicable agreement for further details.
; IP_TOOL_NAME ; LPM_MULT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 2-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; FIFO ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; RAM: 1-PORT ; -- ; -- ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M ; -- ;
; IP_TOOL_NAME ; altera_pll ; -- ; clk100M_0002 ; -- ;
...
...
@@ -107,6 +109,8 @@ applicable agreement for further details.
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M ; -- ;
; IP_TOOL_VERSION ; 13.1 ; -- ; clk100M_0002 ; -- ;
...
...
@@ -125,6 +129,8 @@ applicable agreement for further details.
; MISC_FILE ; clk/clk100M_sim/clk100M.vo ; -- ; -- ; -- ;
; MISC_FILE ; regfile/regfile_2_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; uart/uart_fifo_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; ram/ram16kB_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; ram/ram128kB_bb.v ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
...
...
@@ -140,11 +146,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:
15 ; 1.6 ; 4881 MB ; 00:00:15
;
; Fitter ; 00:0
0:47 ; 1.7 ; 6787 MB ; 00:01:22
;
; Assembler ; 00:00:
09 ; 1.0 ; 4803 MB ; 00:00:0
9 ;
; TimeQuest Timing Analyzer ; 00:00:
14 ; 2.3 ; 5401 MB ; 00:00:25
;
; Total ; 00:0
1:25 ; -- ; -- ; 00:02:11
;
; Analysis & Synthesis ; 00:00:
34 ; 1.0 ; 698 MB ; 00:00:33
;
; Fitter ; 00:0
2:17 ; 1.4 ; 2347 MB ; 00:02:57
;
; Assembler ; 00:00:
19 ; 1.0 ; 673 MB ; 00:00:1
9 ;
; TimeQuest Timing Analyzer ; 00:00:
46 ; 1.5 ; 1179 MB ; 00:01:03
;
; Total ; 00:0
3:56 ; -- ; -- ; 00:04:52
;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
...
...
@@ -153,10 +159,10 @@ applicable agreement for further details.
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ;
DESKTOP-I91JIJO ; Windows 7 ; 6.2
; x86_64 ;
; Fitter ;
DESKTOP-I91JIJO ; Windows 7 ; 6.2
; x86_64 ;
; Assembler ;
DESKTOP-I91JIJO ; Windows 7 ; 6.2
; x86_64 ;
; TimeQuest Timing Analyzer ;
DESKTOP-I91JIJO ; Windows 7 ; 6.2
; x86_64 ;
; Analysis & Synthesis ;
RG6MXLMTA6KAGXI ; Windows 7 ; 6.1
; x86_64 ;
; Fitter ;
RG6MXLMTA6KAGXI ; Windows 7 ; 6.1
; x86_64 ;
; Assembler ;
RG6MXLMTA6KAGXI ; Windows 7 ; 6.1
; x86_64 ;
; TimeQuest Timing Analyzer ;
RG6MXLMTA6KAGXI ; Windows 7 ; 6.1
; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
...
...
examples/hdl4se_riscv/de1/de1_riscv.jdi
浏览文件 @
809d9d8b
<sld_project_info>
<project>
<hash md5_digest_80b="
a10354c7aacc91a72b47
"/>
<hash md5_digest_80b="
347fbbdd10ff5f21590c
"/>
</project>
<file_info>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
...
...
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
浏览文件 @
809d9d8b
因为 它太大了无法显示 source diff 。你可以改为
查看blob
。
examples/hdl4se_riscv/de1/de1_riscv.map.summary
浏览文件 @
809d9d8b
Analysis & Synthesis Status : Successful -
Sun Aug 29 18:51:14
2021
Analysis & Synthesis Status : Successful -
Mon Aug 30 18:40:06
2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 18
57
Total registers : 18
39
Total pins : 204
Total virtual pins : 0
Total block memory bits :
83,465
Total block memory bits :
1,067,744
Total DSP Blocks : 10
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI TX Channels : 0
Total PLLs :
0
Total PLLs :
1
Total DLLs : 0
examples/hdl4se_riscv/de1/de1_riscv.qsf
浏览文件 @
809d9d8b
...
...
@@ -511,4 +511,6 @@ set_global_assignment -name QIP_FILE clk/clk100M.qip
set_global_assignment -name SIP_FILE clk/clk100M.sip
set_global_assignment -name QIP_FILE regfile/regfile_2.qip
set_global_assignment -name QIP_FILE uart/uart_fifo.qip
set_global_assignment -name QIP_FILE ram/ram16kB.qip
set_global_assignment -name QIP_FILE ram/ram128kB.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
examples/hdl4se_riscv/de1/de1_riscv.sof
浏览文件 @
809d9d8b
无法预览此类型文件
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
浏览文件 @
809d9d8b
...
...
@@ -2,52 +2,84 @@
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup '
CLOCK_50
'
Slack :
3.899
Type : Slow 1100mV 85C Model Setup '
clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
'
Slack :
6.023
TNS : 0.000
Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.265
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.242
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.666
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 8.761
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.877
Slack : 9.670
TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 5.710
TNS : 0.000
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.220
TNS : 0.000
Type : Slow 1100mV 0C Model
Setup 'CLOCK_50
'
Slack :
3.693
Type : Slow 1100mV 0C Model
Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
'
Slack :
1.666
TNS : 0.000
Type : Slow 1100mV 0C Model
Hold 'CLOCK_50
'
Slack :
0.255
Type : Slow 1100mV 0C Model
Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
'
Slack :
8.736
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack :
8.902
Slack :
9.673
TNS : 0.000
Type : Fast 1100mV 85C Model Setup '
CLOCK_50
'
Slack : 1
0.143
Type : Fast 1100mV 85C Model Setup '
clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
'
Slack : 1
1.255
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
Slack : 0.166
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.148
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Slack : 1.666
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 8.881
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : 8.476
Slack : 9.336
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 11.824
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.134
TNS : 0.000
Type : Fast 1100mV 0C Model
Setup 'CLOCK_50
'
Slack : 1
0.761
Type : Fast 1100mV 0C Model
Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
'
Slack : 1
.666
TNS : 0.000
Type : Fast 1100mV 0C Model
Hold 'CLOCK_50
'
Slack :
0.145
Type : Fast 1100mV 0C Model
Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
'
Slack :
8.884
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack :
8.433
Slack :
9.286
TNS : 0.000
------------------------------------------------------------
examples/hdl4se_riscv/de1/de1_riscv_v3.v
浏览文件 @
809d9d8b
...
...
@@ -3,7 +3,7 @@
// This code is generated by Terasic System Builder
//=======================================================
`define
USECLOCK50
`define
USECLOCK50
_1
module
de1_riscv
(
...
...
@@ -136,13 +136,13 @@ module de1_riscv(
assign
bReadData
=
((
readaddr
&
32'hffffff00
)
==
32'hF0000000
)
?
bReadDataKey
:
(
((
readaddr
&
32'hff
ffc
000
)
==
32'h00000000
)
?
bReadDataRam
:
(
((
readaddr
&
32'hff
000
000
)
==
32'h00000000
)
?
bReadDataRam
:
(
((
readaddr
&
32'hffffff00
)
==
32'hF0000100
)
?
bReadDataUart
:
(
32'hffffffff
)
)
);
wire
[
10
:
0
]
ramaddr
;
assign
ramaddr
=
wWrite
?
bWriteAddr
[
12
:
2
]
:
bReadAddr
[
12
:
2
];
wire
[
29
:
0
]
ramaddr
;
assign
ramaddr
=
wWrite
?
bWriteAddr
[
31
:
2
]
:
bReadAddr
[
31
:
2
];
wire
[
4
:
0
]
regno
;
wire
[
3
:
0
]
regena
;
...
...
@@ -182,7 +182,7 @@ module de1_riscv(
regfile
regs
(
regno
,
regena
,
wClk
,
regwrdata
,
regwren
,
regrddata
);
regfile
regs2
(
regno2
,
regena2
,
wClk
,
regwrdata2
,
regwren2
,
regrddata2
);
ram
8kb
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
((
bWriteAddr
&
32'hffffc
000
)
==
0
)
?
wWrite
:
1'b0
,
bReadDataRam
);
ram
128kB
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
((
bWriteAddr
&
32'hff000
000
)
==
0
)
?
wWrite
:
1'b0
,
bReadDataRam
);
riscv_core
core
(
wClk
,
nwReset
,
wWrite
,
bWriteAddr
,
bWriteData
,
bWriteMask
,
wRead
,
bReadAddr
,
bReadData
,
regno
,
regena
,
regwrdata
,
regwren
,
(
lastregno
==
0
)
?
0
:
regrddata
,
regno2
,
regena2
,
regwrdata2
,
regwren2
,
(
lastregno2
==
0
)
?
0
:
regrddata2
...
...
examples/hdl4se_riscv/de1/ram/ram128kB.qip
0 → 100644
浏览文件 @
809d9d8b
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram128kB.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram128kB_bb.v"]
examples/hdl4se_riscv/de1/ram/ram128kB.v
0 → 100644
浏览文件 @
809d9d8b
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram128kB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale
1
ps
/
1
ps
// synopsys translate_on
module
ram128kB
(
address
,
byteena
,
clock
,
data
,
wren
,
q
);
input
[
14
:
0
]
address
;
input
[
3
:
0
]
byteena
;
input
clock
;
input
[
31
:
0
]
data
;
input
wren
;
output
[
31
:
0
]
q
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1
[
3
:
0
]
byteena
;
tri1
clock
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire
[
31
:
0
]
sub_wire0
;
wire
[
31
:
0
]
q
=
sub_wire0
[
31
:
0
];
altsyncram
altsyncram_component
(
.
address_a
(
address
),
.
byteena_a
(
byteena
),
.
clock0
(
clock
),
.
data_a
(
data
),
.
wren_a
(
wren
),
.
q_a
(
sub_wire0
),
.
aclr0
(
1'b0
),
.
aclr1
(
1'b0
),
.
address_b
(
1'b1
),
.
addressstall_a
(
1'b0
),
.
addressstall_b
(
1'b0
),
.
byteena_b
(
1'b1
),
.
clock1
(
1'b1
),
.
clocken0
(
1'b1
),
.
clocken1
(
1'b1
),
.
clocken2
(
1'b1
),
.
clocken3
(
1'b1
),
.
data_b
(
1'b1
),
.
eccstatus
(),
.
q_b
(),
.
rden_a
(
1'b1
),
.
rden_b
(
1'b1
),
.
wren_b
(
1'b0
));
defparam
altsyncram_component
.
byte_size
=
8
,
altsyncram_component
.
clock_enable_input_a
=
"BYPASS"
,
altsyncram_component
.
clock_enable_output_a
=
"BYPASS"
,
altsyncram_component
.
init_file
=
"../test_code/test.mif"
,
altsyncram_component
.
intended_device_family
=
"Cyclone V"
,
altsyncram_component
.
lpm_hint
=
"ENABLE_RUNTIME_MOD=NO"
,
altsyncram_component
.
lpm_type
=
"altsyncram"
,
altsyncram_component
.
numwords_a
=
32768
,
altsyncram_component
.
operation_mode
=
"SINGLE_PORT"
,
altsyncram_component
.
outdata_aclr_a
=
"NONE"
,
altsyncram_component
.
outdata_reg_a
=
"UNREGISTERED"
,
altsyncram_component
.
power_up_uninitialized
=
"FALSE"
,
altsyncram_component
.
read_during_write_mode_port_a
=
"NEW_DATA_NO_NBE_READ"
,
altsyncram_component
.
widthad_a
=
15
,
altsyncram_component
.
width_a
=
32
,
altsyncram_component
.
width_byteena_a
=
4
;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/ram/ram128kB_bb.v
0 → 100644
浏览文件 @
809d9d8b
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram128kB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module
ram128kB
(
address
,
byteena
,
clock
,
data
,
wren
,
q
);
input
[
14
:
0
]
address
;
input
[
3
:
0
]
byteena
;
input
clock
;
input
[
31
:
0
]
data
;
input
wren
;
output
[
31
:
0
]
q
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1
[
3
:
0
]
byteena
;
tri1
clock
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram128kB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/ram/ram16kB.qip
0 → 100644
浏览文件 @
809d9d8b
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram16kB.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram16kB_bb.v"]
examples/hdl4se_riscv/de1/ram/ram16kB.v
0 → 100644
浏览文件 @
809d9d8b
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram16kB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale
1
ps
/
1
ps
// synopsys translate_on
module
ram16kB
(
address
,
byteena
,
clock
,
data
,
wren
,
q
);
input
[
11
:
0
]
address
;
input
[
3
:
0
]
byteena
;
input
clock
;
input
[
31
:
0
]
data
;
input
wren
;
output
[
31
:
0
]
q
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1
[
3
:
0
]
byteena
;
tri1
clock
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire
[
31
:
0
]
sub_wire0
;
wire
[
31
:
0
]
q
=
sub_wire0
[
31
:
0
];
altsyncram
altsyncram_component
(
.
address_a
(
address
),
.
byteena_a
(
byteena
),
.
clock0
(
clock
),
.
data_a
(
data
),
.
wren_a
(
wren
),
.
q_a
(
sub_wire0
),
.
aclr0
(
1'b0
),
.
aclr1
(
1'b0
),
.
address_b
(
1'b1
),
.
addressstall_a
(
1'b0
),
.
addressstall_b
(
1'b0
),
.
byteena_b
(
1'b1
),
.
clock1
(
1'b1
),
.
clocken0
(
1'b1
),
.
clocken1
(
1'b1
),
.
clocken2
(
1'b1
),
.
clocken3
(
1'b1
),
.
data_b
(
1'b1
),
.
eccstatus
(),
.
q_b
(),
.
rden_a
(
1'b1
),
.
rden_b
(
1'b1
),
.
wren_b
(
1'b0
));
defparam
altsyncram_component
.
byte_size
=
8
,
altsyncram_component
.
clock_enable_input_a
=
"BYPASS"
,
altsyncram_component
.
clock_enable_output_a
=
"BYPASS"
,
altsyncram_component
.
init_file
=
"../test_code/test.mif"
,
altsyncram_component
.
intended_device_family
=
"Cyclone V"
,
altsyncram_component
.
lpm_hint
=
"ENABLE_RUNTIME_MOD=NO"
,
altsyncram_component
.
lpm_type
=
"altsyncram"
,
altsyncram_component
.
numwords_a
=
4096
,
altsyncram_component
.
operation_mode
=
"SINGLE_PORT"
,
altsyncram_component
.
outdata_aclr_a
=
"NONE"
,
altsyncram_component
.
outdata_reg_a
=
"UNREGISTERED"
,
altsyncram_component
.
power_up_uninitialized
=
"FALSE"
,
altsyncram_component
.
read_during_write_mode_port_a
=
"NEW_DATA_NO_NBE_READ"
,
altsyncram_component
.
widthad_a
=
12
,
altsyncram_component
.
width_a
=
32
,
altsyncram_component
.
width_byteena_a
=
4
;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/ram/ram16kB_bb.v
0 → 100644
浏览文件 @
809d9d8b
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram16kB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module
ram16kB
(
address
,
byteena
,
clock
,
data
,
wren
,
q
);
input
[
11
:
0
]
address
;
input
[
3
:
0
]
byteena
;
input
clock
;
input
[
31
:
0
]
data
;
input
wren
;
output
[
31
:
0
]
q
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1
[
3
:
0
]
byteena
;
tri1
clock
;
`ifndef
ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram16kB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/ram128kB.qip
0 → 100644
浏览文件 @
809d9d8b
examples/hdl4se_riscv/de1/ram16kB.qip
0 → 100644
浏览文件 @
809d9d8b
examples/hdl4se_riscv/de1/test.mif
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
浏览文件 @
809d9d8b
...
...
@@ -90,7 +90,8 @@ module uart_ctrl(
reg
[
15
:
0
]
lastdiv
;
reg
[
15
:
0
]
newdiv
;
reg
[
2
:
0
]
ctrlstate
;
reg
[
7
:
0
]
ctrlstate
;
reg
[
15
:
0
]
waitclk
;
always
@
(
posedge
wClk
)
if
(
~
nwReset
)
begin
uart_read
<=
1'b0
;
...
...
@@ -101,6 +102,7 @@ module uart_ctrl(
recv_buf_data
<=
8'b0
;
uart_write_data
<=
16'b0
;
ctrlstate
<=
0
;
waitclk
<=
0
;
lastdiv
<=
50000000
/
38400
;
end
else
begin
uart_read
<=
1'b0
;
...
...
@@ -123,7 +125,7 @@ module uart_ctrl(
uart_write
<=
1'b1
;
uart_write_data
<=
newdiv
;
lastdiv
<=
newdiv
;
ctrlstate
<=
4
;
ctrlstate
<=
1
;
end
end
else
if
(
ctrlstate
==
1
)
begin
ctrlstate
<=
0
;
...
...
@@ -133,8 +135,6 @@ module uart_ctrl(
recv_buf_data
<=
uart_read_data
[
7
:
0
];
recv_buf_write
<=
1'b1
;
ctrlstate
<=
0
;
end
else
if
(
ctrlstate
==
4
)
begin
ctrlstate
<=
0
;
end
end
...
...
@@ -147,7 +147,7 @@ module uart_ctrl(
[16] -- recv buffer empty
[26:17] -- recv buffer used
*/
assign
ctl_state
=
{
5'b0
,
recv_buf_used
,
recv_buf_empty
,
5'b0
,
send_buf_used
,
send_buf_full
}
;
assign
ctl_state
=
{
4'b0
,
recv_buf_used
,
recv_buf_full
,
recv_buf_empty
,
4'b0
,
send_buf_used
,
send_buf_empty
,
send_buf_full
}
;
/* 读命令处理 */
reg
[
31
:
0
]
readdata
;
...
...
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv.h
浏览文件 @
809d9d8b
...
...
@@ -51,7 +51,7 @@ DEFINE_GUID(CLSID_HDL4SE_RISCV_RAM, 0xee3409b2, 0x6d04, 0x42b3, 0xa4, 0x4d, 0x7f
// {2E577C6B-2FF1-425E-90B3-947EB523B863}
DEFINE_GUID
(
CLSID_HDL4SE_RISCV_REGFILE
,
0x2e577c6b
,
0x2ff1
,
0x425e
,
0x90
,
0xb3
,
0x94
,
0x7e
,
0xb5
,
0x23
,
0xb8
,
0x63
);
#define RAMSIZE
204
8
#define RAMSIZE
3276
8
#endif
...
...
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v3.c
浏览文件 @
809d9d8b
...
...
@@ -92,8 +92,8 @@ enum riscv_core_state {
RISCVSTATE_INIT_REGX2
,
RISCVSTATE_READ_INST
,
RISCVSTATE_READ_REGS
,
RISCVSTATE_WRITE_RD
,
RISCVSTATE_EXEC_INST
,
RISCVSTATE_WRITE_RD
,
RISCVSTATE_WAIT_LD
,
RISCVSTATE_WAIT_ST
,
RISCVSTATE_WAIT_DIV
...
...
@@ -165,6 +165,12 @@ DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, regrddata") {
imm
=
sign_expand
(
imm
,
11
);
rdaddr
=
rs1
+
imm
;
vput
(
ldaddr
,
rdaddr
);
if
(
rdaddr
&
3
)
{
unsigned
int
func3
=
(
instr
>>
12
)
&
0x7
;
if
(
func3
==
2
)
{
printf
(
"read a unaligned addr %08x, %08x, %d, %08x, %08x
\n
"
,
vget
(
pc
),
instr
,
rdaddr
&
3
,
rs1
,
imm
);
}
}
}
}
}
END_DEFINE_FUNC
...
...
@@ -463,7 +469,7 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
case
1
:
v
=
(
v
>>
8
)
&
0xffff
;
break
;
case
2
:
v
=
(
v
>>
16
)
&
0xffff
;
break
;
case
3
:
{
printf
(
"No support for load 16bit in more than one word
\n
"
);
printf
(
"No support for load 16bit in more than one word
[pc=%08x, instr=%08x, ldaddr=%d]
\n
"
,
vget
(
pc
),
instr
,
ldaddr
);
exit
(
-
8
);
}
break
;
}
...
...
@@ -472,7 +478,7 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
break
;
case
2
:
/*lw*/
if
(
ldaddr
!=
0
)
{
printf
(
"No support for load
16bit in more than one word
\n
"
);
printf
(
"No support for load
32bit in more than one word[pc=%08x, instr=%08x, ldaddr=%d]
\n
"
,
vget
(
pc
),
instr
,
ldaddr
);
exit
(
-
9
);
}
RISCV_SETDSTREG
(
readreg
,
v
);
...
...
@@ -492,7 +498,7 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
case
1
:
v
=
(
v
>>
8
)
&
0xffff
;
break
;
case
2
:
v
=
(
v
>>
16
)
&
0xffff
;
break
;
case
3
:
{
printf
(
"No support for load 16bit in more than one word
\n
"
);
printf
(
"No support for load 16bit in more than one word
[pc=%08x, instr=%08x, ldaddr=%d]
\n
"
,
vget
(
pc
),
instr
,
ldaddr
);
exit
(
-
8
);
}
break
;
}
...
...
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
浏览文件 @
809d9d8b
...
...
@@ -133,7 +133,8 @@ DEFINE_FUNC(riscv_ram_setup, "") {
|
(
pobj
->
rambyteena
&
2
?
0x0000ff00
:
0
)
|
(
pobj
->
rambyteena
&
4
?
0x00ff0000
:
0
)
|
(
pobj
->
rambyteena
&
8
?
0xff000000
:
0
);
pobj
->
ram
[
pobj
->
ramaddr
]
=
(
pobj
->
ram
[
pobj
->
ramaddr
]
&
(
~
mask
))
if
(
pobj
->
ramaddr
<
RAMSIZE
)
pobj
->
ram
[
pobj
->
ramaddr
]
=
(
pobj
->
ram
[
pobj
->
ramaddr
]
&
(
~
mask
))
|
(
pobj
->
ramwrdata
&
mask
);
}
pobj
->
ramwren
=
0
;
...
...
@@ -158,28 +159,19 @@ static int loadExecImage(unsigned char* data, int maxlen)
}
else
{
int
len
;
int
i
;
unsigned
int
temp
[
16
];
if
(
addr
>=
maxlen
-
16
)
{
printf
(
"loadExecImage failed, address [%08x] overflow
\n
"
,
addr
);
exit
(
-
5
);
}
len
=
sscanf
(
line
,
"%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X"
,
(
unsigned
int
*
)(
data
+
addr
+
0
),
(
unsigned
int
*
)(
data
+
addr
+
1
),
(
unsigned
int
*
)(
data
+
addr
+
2
),
(
unsigned
int
*
)(
data
+
addr
+
3
),
(
unsigned
int
*
)(
data
+
addr
+
4
),
(
unsigned
int
*
)(
data
+
addr
+
5
),
(
unsigned
int
*
)(
data
+
addr
+
6
),
(
unsigned
int
*
)(
data
+
addr
+
7
),
(
unsigned
int
*
)(
data
+
addr
+
8
),
(
unsigned
int
*
)(
data
+
addr
+
9
),
(
unsigned
int
*
)(
data
+
addr
+
10
),
(
unsigned
int
*
)(
data
+
addr
+
11
),
(
unsigned
int
*
)(
data
+
addr
+
12
),
(
unsigned
int
*
)(
data
+
addr
+
13
),
(
unsigned
int
*
)(
data
+
addr
+
14
),
(
unsigned
int
*
)(
data
+
addr
+
15
)
);
&
temp
[
0
],
&
temp
[
1
],
&
temp
[
2
],
&
temp
[
3
],
&
temp
[
4
],
&
temp
[
5
],
&
temp
[
6
],
&
temp
[
7
],
&
temp
[
8
],
&
temp
[
9
],
&
temp
[
10
],
&
temp
[
11
],
&
temp
[
12
],
&
temp
[
13
],
&
temp
[
14
],
&
temp
[
15
]);
for
(
i
=
0
;
i
<
len
;
i
++
)
data
[
addr
+
i
]
=
temp
[
i
];
addr
+=
len
;
}
}
...
...
@@ -218,11 +210,11 @@ MODULE_INIT(riscv_ram)
pobj
->
ramwren
=
0
;
PORT_IN
(
clock
,
1
);
PORT_IN
(
wren
,
1
);
PORT_IN
(
address
,
11
);
PORT_IN
(
address
,
30
);
PORT_IN
(
data
,
32
);
PORT_IN
(
byteena
,
4
);
GPORT_OUT
(
q
,
32
,
riscv_ram_gen_q
);
REG
(
lastaddr
,
11
);
REG
(
lastaddr
,
30
);
CLKTICK_FUNC
(
riscv_ram_clktick
);
SETUP_FUNC
(
riscv_ram_setup
);
DEINIT_FUNC
(
riscv_ram_deinit
);
...
...
examples/hdl4se_riscv/hdl4se_riscv_sim/main_v2.c
浏览文件 @
809d9d8b
...
...
@@ -99,6 +99,7 @@ int main(int argc, char* argv[])
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"instr"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"state"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"wRead"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"bReadAddr"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"bReadData"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"wWrite"
);
objectCall2
(
vcdfile
,
AddSignal
,
"/top/core"
,
"bWriteAddr"
);
...
...
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v3.c
浏览文件 @
809d9d8b
...
...
@@ -31,7 +31,7 @@
/*
* Created by HDL4SE @
Sun Aug 29 17:30:02
2021
* Created by HDL4SE @
Mon Aug 30 13:49:51
2021
* Don't edit it.
*/
...
...
@@ -59,6 +59,7 @@ IDLIST
VID
(
regrddata
),
VID
(
regrddata2
),
VID
(
ram_dot_byteena
),
/* port:ram(ram8kb).byteena, 1 */
VID
(
ram_dot_wren
),
/* port:ram(ram8kb).wren, 4 */
VID
(
bReadDataRam
),
VID
(
bReadDataKey
),
VID
(
wWrite
),
...
...
@@ -86,24 +87,29 @@ DEFINE_FUNC(top_gen_ram_dot_byteena, "bWriteMask, ") { /* port:ram(ram8kb).bytee
vputs
(
ram_dot_byteena
,
~
(
vgets
(
bWriteMask
)));
}
END_DEFINE_FUNC
DEFINE_FUNC
(
top_gen_ram_dot_wren
,
"bWriteAddr, wWrite, "
)
{
/* port:ram(ram8kb).wren, 4 */
vputs
(
ram_dot_wren
,
(((
vgets
(
bWriteAddr
))
&
(
0xff000000
))
==
(
0
))
?
(
vgets
(
wWrite
))
:
(
0
));
}
END_DEFINE_FUNC
DEFINE_FUNC
(
top_gen_bReadData
,
"bReadAddr_out, bReadDataKey, bReadDataRam, "
)
{
vputs
(
bReadData
,
(((
vgets
(
bReadAddr_out
))
&
(
0xffffff00
))
==
(
0xf0000000
))
?
(
vgets
(
bReadDataKey
))
:
((((
vgets
(
bReadAddr_out
))
&
(
0xff
ffc
000
))
==
(
0
))
?
(
vgets
(
bReadDataRam
))
:
(
0xffffffff
)));
vputs
(
bReadData
,
(((
vgets
(
bReadAddr_out
))
&
(
0xffffff00
))
==
(
0xf0000000
))
?
(
vgets
(
bReadDataKey
))
:
((((
vgets
(
bReadAddr_out
))
&
(
0xff
000
000
))
==
(
0
))
?
(
vgets
(
bReadDataRam
))
:
(
0xffffffff
)));
}
END_DEFINE_FUNC
DEFINE_FUNC
(
top_gen_ramaddr
,
"wWrite, bWriteAddr, bReadAddr, "
)
{
vputs
(
ramaddr
,
(
vgets
(
wWrite
))
?
((
vget
(
bWriteAddr
)
>>
2
)
&
0x
7ff
)
:
((
vget
(
bReadAddr
)
>>
2
)
&
0x7
ff
));
vputs
(
ramaddr
,
(
vgets
(
wWrite
))
?
((
vget
(
bWriteAddr
)
>>
2
)
&
0x
3fffffff
)
:
((
vget
(
bReadAddr
)
>>
2
)
&
0x3fffff
ff
));
}
END_DEFINE_FUNC
GEN_MODULE_INIT
PORT_IN
(
wClk
,
1
);
PORT_IN
(
nwReset
,
1
);
WIRE
(
bReadData
,
32
);
WIRE
(
ramaddr
,
11
);
WIRE
(
ramaddr
,
30
);
WIRE
(
wRead_out
,
1
);
WIRE
(
bReadAddr_out
,
32
);
WIRE
(
regrddata
,
32
);
WIRE
(
regrddata2
,
32
);
WIRE
(
ram_dot_byteena
,
1
);
WIRE
(
ram_dot_wren
,
1
);
WIRE
(
bReadDataRam
,
32
);
WIRE
(
bReadDataKey
,
32
);
WIRE
(
wWrite
,
1
);
...
...
@@ -139,7 +145,7 @@ GEN_MODULE_INIT
CELL_INST
(
"EE3409B2-6D04-42B3-A44D-7F2444DDC00D"
,
/* ram8kb */
"ram"
,
""
,
"ramaddr, ram_dot_byteena, wClk, bWriteData,
wWrite
, bReadDataRam"
);
"ramaddr, ram_dot_byteena, wClk, bWriteData,
ram_dot_wren
, bReadDataRam"
);
CELL_INST
(
"2925e2cf-dd49-4155-b31d-41d48f0f98dc"
,
/* digitled */
"led"
,
""
,
...
...
@@ -151,6 +157,7 @@ GEN_MODULE_INIT
", regno, regena, regwrdata, regwren, regrddata, regno2, regena2, regwrdata2, regwren2"
", regrddata2"
);
GEN_FUNC
(
"ram_dot_byteena"
,
top_gen_ram_dot_byteena
);
GEN_FUNC
(
"ram_dot_wren"
,
top_gen_ram_dot_wren
);
GEN_FUNC
(
"bReadData"
,
top_gen_bReadData
);
GEN_FUNC
(
"ramaddr"
,
top_gen_ramaddr
);
END_GEN_MODULE_INIT
...
...
examples/hdl4se_riscv/test_code/main_v2.c
浏览文件 @
809d9d8b
#include <stdio.h>
#define UARTADDRESS (unsigned int *)0xf0000100
/*
...
...
@@ -11,24 +10,26 @@
[16] -- recv buffer empty
[26:17] -- recv buffer used
*/
/*
int _write(int fd, char* buf, int len)
int
uart_write
(
char
*
buf
,
int
len
)
{
volatile
int
j
;
volatile
unsigned
int
*
uart
=
UARTADDRESS
;
unsigned
int
state
;
int
i
;
i
=
0
;
while
(
i
<
len
)
{
state
=
uart
[
2
];
if ((state &
1) =
= 0) {
uart[1] =
(unsigned int)(unsigned char)
buf[i];
if
((
state
&
2
)
!
=
0
)
{
uart
[
1
]
=
buf
[
i
];
i
++
;
}
}
return
len
;
}
int
_read(int fd,
char* buf, int len)
int
uart_read
(
char
*
buf
,
int
len
)
{
volatile
unsigned
int
*
uart
=
UARTADDRESS
;
unsigned
int
state
;
...
...
@@ -38,20 +39,21 @@ int _read(int fd, char* buf, int len)
i
=
0
;
do
{
state
=
uart
[
2
];
if (
(state & (1 << 16)) == 0) {
if
((
state
&
(
1
<<
16
))
==
0
)
{
state
>>=
17
;
if (state == 0)
continue;
if
(
len
>
state
)
len
=
state
;
for (i = 0; i < len; i++) {
buf[i] = uart[0];
for
(
i
=
0
;
i
<
len
;
i
++
)
{
buf
[
i
]
=
uart
[
0
];
}
}
else
{
return
0
;
}
}
while
(
i
==
0
);
return
i
;
}
*/
const
unsigned
int
segcode
[
10
]
=
{
0x3F
,
...
...
@@ -71,10 +73,51 @@ unsigned int num2seg(unsigned int num)
return
segcode
[
num
%
10
];
}
int
int2s
(
char
*
buf
,
int
num
)
{
int
i
;
int
len
;
int
sign
;
len
=
0
;
sign
=
0
;
if
(
num
<
0
)
{
num
=
-
num
;
sign
=
0
;
}
while
(
num
>
0
)
{
buf
[
len
++
]
=
(
num
%
10
)
+
'0'
;
num
/=
10
;
}
if
(
sign
)
buf
[
len
++
]
=
'-'
;
for
(
i
=
0
;
i
<
len
/
2
;
i
++
)
{
int
di
=
len
-
1
-
i
;
char
temp
;
temp
=
buf
[
i
];
buf
[
i
]
=
buf
[
di
];
buf
[
di
]
=
temp
;
}
buf
[
len
]
=
0
;
return
len
;
}
int
_strcat
(
char
*
s
,
const
char
*
t
)
{
char
*
ss
=
s
;
while
(
*
s
)
s
++
;
while
(
*
t
)
*
s
++
=
*
t
++
;
*
s
++
=
0
;
return
s
-
ss
;
}
int
main
(
int
argc
,
char
*
argv
[])
{
unsigned
long
long
count
,
ctemp
;
long
recvcount
,
recvcountseg
;
int
countit
=
1
;
volatile
unsigned
int
*
ledkey
=
(
unsigned
int
*
)
0xF0000000
;
volatile
unsigned
int
*
leddata
=
(
unsigned
int
*
)
0xf0000010
;
volatile
unsigned
int
*
uart
=
UARTADDRESS
;
...
...
@@ -82,27 +125,27 @@ int main(int argc, char* argv[])
leddata
[
0
]
=
0x6f7f077d
;
leddata
[
1
]
=
0x6d664f5b
;
uart
[
4
]
=
50000000
/
115200
;
recvcount
=
0
;
recvcountseg
=
0
;
do
{
unsigned
int
key
;
unsigned
int
uartstate
;
#if 0
uartstate = uart[2];
if (uartstate & 0x80) { /*rrdy*/
uart[1] = uart[0]; /* writeback */
uart[2] = 0;
continue;
char
buf
[
256
];
char
*
msg
=
"Hello, World!"
;
int
len
;
#if 1
len
=
uart_read
(
buf
,
255
);
if
(
len
>
0
)
{
uart_write
(
buf
,
len
);
recvcount
+=
len
;
recvcountseg
+=
len
;
}
#else
uartstate
=
uart
[
2
];
if
((
uartstate
&
0x10000
)
==
0
)
{
unsigned
int
uartdata
;
uartdata
=
uart
[
0
];
if
(
uartdata
&
0x80000000
)
{
uart
[
1
]
=
'#'
;
}
uart
[
1
]
=
uartdata
;
continue
;
if
(
recvcountseg
>=
1000
)
{
int
i
;
int
len
;
len
=
int2s
(
buf
,
recvcount
);
len
=
_strcat
(
buf
,
" bytes received
\r\n
"
);
uart_write
(
buf
,
len
);
recvcountseg
=
0
;
}
#endif
key
=
*
ledkey
;
...
...
@@ -126,7 +169,7 @@ int main(int argc, char* argv[])
if
(
countit
)
count
++
;
ctemp
=
count
;
ctemp
=
recvcountseg
;
//
count;
leddata
[
0
]
=
num2seg
(
ctemp
)
|
((
num2seg
(
ctemp
/
10ll
))
<<
8
)
|
((
num2seg
(
ctemp
/
100ll
))
<<
16
)
|
...
...
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.elf
浏览文件 @
809d9d8b
无法预览此类型文件
examples/hdl4se_riscv/test_code/test.hex
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.info
浏览文件 @
809d9d8b
...
...
@@ -10,40 +10,39 @@ ELF Header:
Version: 0x1
Entry point address: 0x8c
Start of program headers: 52 (bytes into file)
Start of section headers: 1
585
2 (bytes into file)
Start of section headers: 1
659
2 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 2
Size of section headers: 40 (bytes)
Number of section headers: 2
3
Section header string table index: 2
2
Number of section headers: 2
2
Section header string table index: 2
1
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000074 000074 000d5c 00 AX 0 0 4
[ 2] .rodata PROGBITS 00000dd0 000dd0 000128 00 A 0 0 4
[ 3] .eh_frame PROGBITS 00001000 001000 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 0000102c 00102c 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00001034 001034 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00001038 001038 000428 00 WA 0 0 8
[ 7] .got PROGBITS 00001460 001460 000010 04 WA 0 0 4
[ 8] .sdata PROGBITS 00001470 001470 00000c 00 WA 0 0 4
[ 9] .bss NOBITS 0000147c 00147c 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 00147c 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 00148e 000021 00 0 0 1
[12] .debug_aranges PROGBITS 00000000 0014af 000038 00 0 0 1
[13] .debug_info PROGBITS 00000000 0014e7 000839 00 0 0 1
[14] .debug_abbrev PROGBITS 00000000 001d20 000216 00 0 0 1
[15] .debug_line PROGBITS 00000000 001f36 000766 00 0 0 1
[16] .debug_str PROGBITS 00000000 00269c 000296 01 MS 0 0 1
[17] .debug_line_str PROGBITS 00000000 002932 0000b0 01 MS 0 0 1
[18] .debug_loclists PROGBITS 00000000 0029e2 000a99 00 0 0 1
[19] .debug_rnglists PROGBITS 00000000 00347b 000111 00 0 0 1
[20] .symtab SYMTAB 00000000 00358c 0004d0 10 21 52 4
[21] .strtab STRTAB 00000000 003a5c 0002a3 00 0 0 1
[22] .shstrtab STRTAB 00000000 003cff 0000ed 00 0 0 1
[ 1] .text PROGBITS 00000074 000074 001104 00 AX 0 0 4
[ 2] .rodata PROGBITS 00001178 001178 00014c 00 A 0 0 4
[ 3] .eh_frame PROGBITS 000022c4 0012c4 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 000022f0 0012f0 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 000022f8 0012f8 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00002300 001300 000428 00 WA 0 0 8
[ 7] .sdata PROGBITS 00002728 001728 00000c 00 WA 0 0 4
[ 8] .bss NOBITS 00002734 001734 00001c 00 WA 0 0 4
[ 9] .comment PROGBITS 00000000 001734 000012 01 MS 0 0 1
[10] .riscv.attributes RISCV_ATTRIBUTE 00000000 001746 000026 00 0 0 1
[11] .debug_aranges PROGBITS 00000000 00176c 000038 00 0 0 1
[12] .debug_info PROGBITS 00000000 0017a4 000839 00 0 0 1
[13] .debug_abbrev PROGBITS 00000000 001fdd 000216 00 0 0 1
[14] .debug_line PROGBITS 00000000 0021f3 000766 00 0 0 1
[15] .debug_str PROGBITS 00000000 002959 00029a 01 MS 0 0 1
[16] .debug_line_str PROGBITS 00000000 002bf3 0000aa 01 MS 0 0 1
[17] .debug_loclists PROGBITS 00000000 002c9d 000a99 00 0 0 1
[18] .debug_rnglists PROGBITS 00000000 003736 000111 00 0 0 1
[19] .symtab SYMTAB 00000000 003848 0004f0 10 20 50 4
[20] .strtab STRTAB 00000000 003d38 0002b0 00 0 0 1
[21] .shstrtab STRTAB 00000000 003fe8 0000e8 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
...
...
@@ -54,13 +53,13 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000000 0x00000000 0x00000000 0x0
0ef8 0x00ef8
R E 0x1000
LOAD 0x001
000 0x00001000 0x00001000 0x0047c 0x00498
RW 0x1000
LOAD 0x000000 0x00000000 0x00000000 0x0
12c4 0x012c4
R E 0x1000
LOAD 0x001
2c4 0x000022c4 0x000022c4 0x00470 0x0048c
RW 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .rodata
01 .eh_frame .init_array .fini_array .data .
got .
sdata .bss
01 .eh_frame .init_array .fini_array .data .sdata .bss
There is no dynamic section in this file.
...
...
@@ -68,88 +67,90 @@ There are no relocations in this file.
The decoding of unwind sections for machine type RISC-V is not currently supported.
Symbol table '.symtab' contains 7
7
entries:
Symbol table '.symtab' contains 7
9
entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000074 0 SECTION LOCAL DEFAULT 1 .text
2: 0000
0dd0
0 SECTION LOCAL DEFAULT 2 .rodata
3: 0000
1000
0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 0000
102c
0 SECTION LOCAL DEFAULT 4 .init_array
5: 0000
1034
0 SECTION LOCAL DEFAULT 5 .fini_array
6: 0000
1038
0 SECTION LOCAL DEFAULT 6 .data
7: 0000
1460 0 SECTION LOCAL DEFAULT 7 .got
8: 0000
1470 0 SECTION LOCAL DEFAULT 8 .sdata
9: 0000
147c 0 SECTION LOCAL DEFAULT 9 .bss
10: 00000000 0 SECTION LOCAL DEFAULT 10 .
comment
11: 00000000 0 SECTION LOCAL DEFAULT 11 .
riscv.attribut
es
12: 00000000 0 SECTION LOCAL DEFAULT 12 .debug_
aranges
13: 00000000 0 SECTION LOCAL DEFAULT 13 .debug_
info
14: 00000000 0 SECTION LOCAL DEFAULT 14 .debug_
abbrev
15: 00000000 0 SECTION LOCAL DEFAULT 15 .debug_
line
16: 00000000 0 SECTION LOCAL DEFAULT 16 .debug_str
17: 00000000 0 SECTION LOCAL DEFAULT 17 .debug_l
ine_str
18: 00000000 0 SECTION LOCAL DEFAULT 18 .debug_
loc
lists
19: 00000000 0
SECTION LOCAL DEFAULT 19 .debug_rnglists
20: 000000
00 0 FILE LOCAL DEFAULT ABS __call_atexit.c
21: 000000
74 24 FUNC LOCAL DEFAULT 1 register_fini
22: 0000
0000 0 FILE LOCAL DEFAULT ABS crtstuff.c
23: 0000
1000 0 OBJECT LOCAL DEFAULT 3 __EH_FRAME_BEGIN__
24: 0000
00d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux
25: 0000
147c 1 OBJECT LOCAL DEFAULT 9 completed.1
26: 0000
1034 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
27: 0000
011c 0 FUNC LOCAL DEFAULT 1 frame_dummy
28: 0000
1480 24 OBJECT LOCAL DEFAULT 9 object.0
29: 0000
1030 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
30: 00000000 0 FILE LOCAL DEFAULT ABS
main_v
2.c
2: 0000
1178
0 SECTION LOCAL DEFAULT 2 .rodata
3: 0000
22c4
0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 0000
22f0
0 SECTION LOCAL DEFAULT 4 .init_array
5: 0000
22f8
0 SECTION LOCAL DEFAULT 5 .fini_array
6: 0000
2300
0 SECTION LOCAL DEFAULT 6 .data
7: 0000
2728 0 SECTION LOCAL DEFAULT 7 .sdata
8: 0000
2734 0 SECTION LOCAL DEFAULT 8 .bss
9: 0000
0000 0 SECTION LOCAL DEFAULT 9 .comment
10: 00000000 0 SECTION LOCAL DEFAULT 10 .
riscv.attributes
11: 00000000 0 SECTION LOCAL DEFAULT 11 .
debug_arang
es
12: 00000000 0 SECTION LOCAL DEFAULT 12 .debug_
info
13: 00000000 0 SECTION LOCAL DEFAULT 13 .debug_
abbrev
14: 00000000 0 SECTION LOCAL DEFAULT 14 .debug_
line
15: 00000000 0 SECTION LOCAL DEFAULT 15 .debug_
str
16: 00000000 0 SECTION LOCAL DEFAULT 16 .debug_
line_
str
17: 00000000 0 SECTION LOCAL DEFAULT 17 .debug_l
oclists
18: 00000000 0 SECTION LOCAL DEFAULT 18 .debug_
rng
lists
19: 00000000 0
FILE LOCAL DEFAULT ABS __call_atexit.c
20: 000000
74 24 FUNC LOCAL DEFAULT 1 register_fini
21: 000000
00 0 FILE LOCAL DEFAULT ABS crtstuff.c
22: 0000
22c4 0 OBJECT LOCAL DEFAULT 3 __EH_FRAME_BEGIN__
23: 0000
00d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux
24: 0000
2734 1 OBJECT LOCAL DEFAULT 8 completed.1
25: 0000
22f8 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
26: 0000
011c 0 FUNC LOCAL DEFAULT 1 frame_dummy
27: 0000
2738 24 OBJECT LOCAL DEFAULT 8 object.0
28: 0000
22f4 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
29: 0000
0000 0 FILE LOCAL DEFAULT ABS main_v2.c
30: 00000000 0 FILE LOCAL DEFAULT ABS
libgcc
2.c
31: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
32: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
33: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
34: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
35: 00001038 1064 OBJECT LOCAL DEFAULT 6 impure_data
36: 00000000 0 FILE LOCAL DEFAULT ABS init.c
37: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
38: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
39: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
40: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
41: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
42: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
43: 00001028 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
44: 00000000 0 FILE LOCAL DEFAULT ABS
45: 00001038 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
46: 00001034 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
47: 00001034 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
48: 0000102c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
49: 00001468 0 OBJECT LOCAL DEFAULT 7 _GLOBAL_OFFSET_TABLE_
50: 0000102c 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
51: 0000102c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
52: 00001838 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
53: 00000dd0 40 OBJECT GLOBAL DEFAULT 2 segcode
54: 00000dc8 8 FUNC GLOBAL DEFAULT 1 __errno
55: 00001470 0 NOTYPE GLOBAL DEFAULT 8 __SDATA_BEGIN__
56: 00001474 0 OBJECT GLOBAL HIDDEN 8 __dso_handle
57: 00001470 4 OBJECT GLOBAL DEFAULT 8 _global_impure_ptr
58: 000009f8 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
59: 00000598 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
60: 00000c90 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
61: 00000b70 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
62: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
63: 00000d00 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
64: 00001498 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
65: 0000147c 0 NOTYPE GLOBAL DEFAULT 9 __bss_start
66: 00000a94 220 FUNC GLOBAL DEFAULT 1 memset
67: 0000017c 1052 FUNC GLOBAL DEFAULT 1 main
68: 00000df8 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
69: 00000cec 20 FUNC GLOBAL DEFAULT 1 atexit
70: 00001478 4 OBJECT GLOBAL DEFAULT 8 _impure_ptr
71: 00001038 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
72: 0000013c 64 FUNC GLOBAL DEFAULT 1 num2seg
73: 0000147c 0 NOTYPE GLOBAL DEFAULT 8 _edata
74: 00001498 0 NOTYPE GLOBAL DEFAULT 9 _end
75: 000009c8 48 FUNC GLOBAL DEFAULT 1 exit
76: 00000d98 48 FUNC GLOBAL DEFAULT 1 _exit
32: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
33: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
34: 00002300 1064 OBJECT LOCAL DEFAULT 6 impure_data
35: 00000000 0 FILE LOCAL DEFAULT ABS init.c
36: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
37: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
38: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
39: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
40: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
41: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
42: 000022ec 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
43: 00000000 0 FILE LOCAL DEFAULT ABS
44: 000022fc 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
45: 000022f8 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
46: 000022f8 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
47: 000022f0 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
48: 000022f0 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
49: 000022f0 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
50: 0000043c 148 FUNC GLOBAL DEFAULT 1 _strcat
51: 00002b00 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
52: 00001178 40 OBJECT GLOBAL DEFAULT 2 segcode
53: 00001170 8 FUNC GLOBAL DEFAULT 1 __errno
54: 00002728 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__
55: 0000013c 140 FUNC GLOBAL DEFAULT 1 uart_write
56: 0000272c 0 OBJECT GLOBAL HIDDEN 7 __dso_handle
57: 00002728 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr
58: 00000da0 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
59: 00000940 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
60: 00001038 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
61: 000002e0 348 FUNC GLOBAL DEFAULT 1 int2s
62: 00000f18 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
63: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
64: 000010a8 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
65: 00002750 0 NOTYPE GLOBAL DEFAULT 8 __BSS_END__
66: 00002734 0 NOTYPE GLOBAL DEFAULT 8 __bss_start
67: 00000e3c 220 FUNC GLOBAL DEFAULT 1 memset
68: 000004d0 1136 FUNC GLOBAL DEFAULT 1 main
69: 000011c4 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
70: 00001094 20 FUNC GLOBAL DEFAULT 1 atexit
71: 00002730 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr
72: 00002300 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
73: 000002a0 64 FUNC GLOBAL DEFAULT 1 num2seg
74: 00002734 0 NOTYPE GLOBAL DEFAULT 7 _edata
75: 00002750 0 NOTYPE GLOBAL DEFAULT 8 _end
76: 000001c8 216 FUNC GLOBAL DEFAULT 1 uart_read
77: 00000d70 48 FUNC GLOBAL DEFAULT 1 exit
78: 00001140 48 FUNC GLOBAL DEFAULT 1 _exit
No version information found in this file.
Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_arch: "rv32i2p0_m2p0
_a2p0
"
examples/hdl4se_riscv/test_code/test.mif
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.sh
浏览文件 @
809d9d8b
...
...
@@ -3,5 +3,5 @@ riscv32-unknown-elf-gcc -Wl,-Ttest.ld main_v2.c -o test.elf
riscv32-unknown-elf-objcopy test.elf
-O
ihex test.hex
riscv32-unknown-elf-objcopy test.elf
-O
verilog test.cod
riscv32-unknown-elf-objdump
-D
-M
no-aliases,numeric test.elf
>
test.txt
riscv32-unk
onwn
-readelf
-a
test.elf
>
test.info
riscv32-unk
nown-elf
-readelf
-a
test.elf
>
test.info
examples/hdl4se_riscv/test_code/test.txt
浏览文件 @
809d9d8b
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/verilog/riscv_core_v3.v
浏览文件 @
809d9d8b
...
...
@@ -35,13 +35,13 @@
`define
RISCVSTATE_INIT_REGX2 1
`define
RISCVSTATE_READ_INST 2
`define
RISCVSTATE_READ_REGS 3
`define
RISCVSTATE_
WRITE_RD
4
`define
RISCVSTATE_
EXEC_INST
5
`define
RISCVSTATE_
EXEC_INST
4
`define
RISCVSTATE_
WRITE_RD
5
`define
RISCVSTATE_WAIT_LD 6
`define
RISCVSTATE_WAIT_ST 7
`define
RISCVSTATE_WAIT_DIV 8
`define
RAMSIZE
204
8
`define
RAMSIZE
3276
8
(
*
HDL4SE
=
"LCOM"
,
...
...
@@ -92,8 +92,8 @@ module riscv_core(
wire
[
4
:
0
]
rd
=
instr
[
11
:
7
];
wire
[
2
:
0
]
func3
=
instr
[
14
:
12
];
reg
cond
;
wire
signed
[
31
:
0
]
rs1
=
regrddata
;
wire
signed
[
31
:
0
]
rs2
=
regrddata2
;
wire
[
31
:
0
]
rs1
=
regrddata
;
wire
[
31
:
0
]
rs2
=
regrddata2
;
wire
signed
[
31
:
0
]
rs1_s
=
rs1
;
wire
signed
[
31
:
0
]
rs2_s
=
rs2
;
wire
signed
[
31
:
0
]
imm_s
=
imm
;
...
...
examples/hdl4se_riscv/verilog/riscv_sim_dump_v3.v
浏览文件 @
809d9d8b
...
...
@@ -24,13 +24,15 @@ module riscv_core
output
reg
[
32'h3
:
32'h0
]
regena2
,
output
reg
[
32'h1f
:
32'h0
]
regwrdata2
,
output
reg
regwren2
,
input
[
32'h1f
:
32'h0
]
regrddata
input
[
32'h1f
:
32'h0
]
regrddata
2
)
;
wire
[
32'h4
:
32'h0
]
opcode
;
wire
[
32'h4
:
32'h0
]
rd
;
wire
[
32'h2
:
32'h0
]
func3
;
wire
[
32'h1f
:
32'h0
]
rs1
;
wire
[
32'h1f
:
32'h0
]
rs2
;
wire
[
32'h1f
:
32'h0
]
rs1_s
;
wire
[
32'h1f
:
32'h0
]
rs2_s
;
wire
[
32'h1f
:
32'h0
]
imm_s
;
...
...
@@ -51,13 +53,15 @@ module riscv_core
assign
bWriteAddr
=
writeaddr
;
assign
bWriteData
=
writedata
;
assign
bWriteMask
=
writemask
;
assign
div_result
=
(((
rs2
==
32'h0
))
?
(
32'hffffffff
)
:
(
div_result_r
))
;
assign
divs_result
=
(((
rs2
==
32'h0
))
?
(
32'hffffffff
)
:
(
divs_result_r
))
;
assign
mod_result
=
(((
rs2
==
32'h0
))
?
(
rs1
)
:
(
mod_result_r
))
;
assign
mods_result
=
(((
rs2
==
32'h0
))
?
(
rs1
)
:
(
mods_result_r
))
;
assign
div_result
=
div_result_r
;
assign
divs_result
=
divs_result_r
;
assign
mod_result
=
mod_result_r
;
assign
mods_result
=
mods_result_r
;
assign
opcode
=
instr
[
6
:
2
]
;
assign
rd
=
instr
[
11
:
7
]
;
assign
func3
=
instr
[
14
:
12
]
;
assign
rs1
=
regrddata
;
assign
rs2
=
regrddata2
;
assign
rs1_s
=
rs1
;
assign
rs2_s
=
rs2
;
assign
imm_s
=
imm
;
...
...
@@ -86,7 +90,7 @@ module riscv_core
end
else
begin
if
((
state
==
7
))
if
((
state
==
4
))
begin
case
(
opcode
)
5'h1b
:
pc
<=
(
pc
+
imm
);
...
...
@@ -101,22 +105,16 @@ module riscv_core
if
((
state
==
3
))
instr
<=
bReadData
;
always
@
(
posedge
wClk
)
if
((
state
==
7
))
if
((
state
==
4
))
if
((
opcode
==
5'h00
))
readreg
<=
rd
;
always
@
(
posedge
wClk
)
if
((
state
==
4
))
rs1
<=
regrddata
;
always
@
(
posedge
wClk
)
if
((
state
==
5
))
rs2
<=
regrddata
;
always
@
(
posedge
wClk
)
if
((
!
(
nwReset
)))
begin
write
<=
0
;
end
else
if
((
state
==
7
))
if
((
state
==
4
))
begin
write
<=
0
;
if
((
opcode
==
5'h08
))
...
...
@@ -184,29 +182,27 @@ module riscv_core
1
:
state
<=
2
;
2
:
state
<=
3
;
3
:
state
<=
4
;
4
:
state
<=
5
;
5
:
state
<=
7
;
6
:
state
<=
2
;
7
:
begin
5
:
state
<=
2
;
4
:
begin
if
((
opcode
==
5'h00
))
state
<=
8
;
state
<=
6
;
else
if
((
opcode
==
5'h08
))
state
<=
9
;
state
<=
7
;
else
if
((((
opcode
==
5'h0c
)
&&
instr
[
25
]
)
&&
func3
[
2
]
))
if
((((
(
opcode
==
5'h0c
)
&&
instr
[
25
]
)
&&
func3
[
2
]
)
&&
(
rs2
!=
0
)
))
begin
state
<=
10
;
state
<=
8
;
divclk
<=
11
;
end
else
state
<=
6
;
state
<=
5
;
end
8
:
state
<=
6
;
9
:
state
<=
2
;
10
:
begin
6
:
state
<=
5
;
7
:
state
<=
2
;
8
:
begin
if
((
divclk
==
0
))
state
<=
6
;
state
<=
5
;
else
divclk
<=
(
divclk
-
1
);
end
...
...
@@ -214,17 +210,17 @@ module riscv_core
end
always
@
(
posedge
wClk
)
if
((
state
==
4
))
if
((
state
==
3
))
begin
case
(
opcode
)
5'h0d
:
imm
<=
{
instr
[
31
:
12
]
,
12'b0
}
;
5'h05
:
imm
<=
{
instr
[
31
:
12
]
,
12'b0
}
;
5'h1b
:
imm
<=
{{
12
{
instr
[
31
]
}{
,
instr
[
19
:
12
]
,
instr
[
20
]
,
instr
[
30
:
21
]
,
1'b0
}
;
5'h19
:
imm
<=
{{
20
{
instr
[
31
]
}{
,
instr
[
31
:
20
]
}
;
5'h18
:
imm
<=
{{
20
{
instr
[
31
]
}{
,
instr
[
7
]
,
instr
[
30
:
25
]
,
instr
[
11
:
8
]
,
1'b0
}
;
5'h00
:
imm
<=
{{
20
{
instr
[
31
]
}{
,
instr
[
31
:
20
]
}
;
5'h08
:
imm
<=
{{
20
{
instr
[
31
]
}{
,
instr
[
31
:
25
]
,
instr
[
11
:
7
]
}
;
5'h04
:
imm
<=
{{
20
{
instr
[
31
]
}{
,
instr
[
31
:
20
]
}
;
case
(
bReadData
[
6
:
2
]
)
5'h0d
:
imm
<=
{
bReadData
[
31
:
12
]
,
12'b0
}
;
5'h05
:
imm
<=
{
bReadData
[
31
:
12
]
,
12'b0
}
;
5'h1b
:
imm
<=
{{
12
{
bReadData
[
31
]
}{
,
bReadData
[
19
:
12
]
,
bReadData
[
20
]
,
bReadData
[
30
:
21
]
,
1'b0
}
;
5'h19
:
imm
<=
{{
20
{
bReadData
[
31
]
}{
,
bReadData
[
31
:
20
]
}
;
5'h18
:
imm
<=
{{
20
{
bReadData
[
31
]
}{
,
bReadData
[
7
]
,
bReadData
[
30
:
25
]
,
bReadData
[
11
:
8
]
,
1'b0
}
;
5'h00
:
imm
<=
{{
20
{
bReadData
[
31
]
}{
,
bReadData
[
31
:
20
]
}
;
5'h08
:
imm
<=
{{
20
{
bReadData
[
31
]
}{
,
bReadData
[
31
:
25
]
,
bReadData
[
11
:
7
]
}
;
5'h04
:
imm
<=
{{
20
{
bReadData
[
31
]
}{
,
bReadData
[
31
:
20
]
}
;
endcase
end
...
...
@@ -235,36 +231,50 @@ module riscv_core
regwren
=
0
;
regena
=
0
;
regwrdata
=
0
;
regno2
=
bReadData
[
24
:
20
]
;
regwren2
=
0
;
regena2
=
0
;
regwrdata2
=
0
;
end
4
:
begin
regno
=
instr
[
24
:
20
]
;
regwren
=
0
;
regena
=
0
;
regwrdata
=
0
;
end
6
:
begin
5
:
begin
regwren
=
(((
dstreg
!=
0
))
?
(
1
)
:
(
0
));
regno
=
dstreg
;
regena
=
4'hf
;
regwrdata
=
dstvalue
;
regwren2
=
(((
dstreg
!=
0
))
?
(
1
)
:
(
0
));
regno2
=
dstreg
;
regena2
=
4'hf
;
regwrdata2
=
dstvalue
;
end
0
:
begin
regwren
=
1
;
regno
=
1
;
regena
=
4'hf
;
regwrdata
=
32'h8c
;
regwren2
=
1
;
regno2
=
1
;
regena2
=
4'hf
;
regwrdata2
=
32'h8c
;
end
1
:
begin
regwren
=
1
;
regno
=
2
;
regena
=
4'hf
;
regwrdata
=
((
2048
*
4
)
-
16
);
regwrdata
=
((
32768
*
4
)
-
16
);
regwren2
=
1
;
regno2
=
2
;
regena2
=
4'hf
;
regwrdata2
=
((
32768
*
4
)
-
16
);
end
default:
begin
regwren
=
0
;
regno
=
0
;
regena
=
0
;
regwrdata
=
0
;
regwren2
=
0
;
regno2
=
0
;
regena2
=
0
;
regwrdata2
=
0
;
end
endcase
...
...
@@ -274,7 +284,7 @@ module riscv_core
ldaddr
<=
pc
;
end
else
if
((
state
==
7
))
if
((
state
==
4
))
begin
if
((
opcode
==
5'h00
))
begin
...
...
@@ -283,7 +293,7 @@ module riscv_core
end
always
@
(
posedge
wClk
)
case
(
state
)
8
:
begin
6
:
begin
dstreg
<=
readreg
;
case
(
func3
)
0
:
begin
...
...
@@ -326,42 +336,30 @@ module riscv_core
endcase
end
10
:
if
((
divclk
==
0
))
8
:
if
((
divclk
==
0
))
begin
dstreg
<=
0
;
case
(
func3
[
1
:
0
]
)
0
:
begin
dstreg
<=
rd
;
if
((
rs2
==
0
))
dstvalue
<=
32'hffffffff
;
else
dstvalue
<=
divs_result
;
end
1
:
begin
dstreg
<=
rd
;
if
((
rs2
==
0
))
dstvalue
<=
32'hffffffff
;
else
dstvalue
<=
div_result
;
end
2
:
begin
dstreg
<=
rd
;
if
((
rs2
==
0
))
dstvalue
<=
rs1
;
else
dstvalue
<=
mods_result
;
end
3
:
begin
dstreg
<=
rd
;
if
((
rs2
==
0
))
dstvalue
<=
rs1
;
else
dstvalue
<=
mod_result
;
end
endcase
end
7
:
begin
4
:
begin
dstreg
<=
rd
;
case
(
opcode
)
5'h0d
:
begin
...
...
@@ -410,20 +408,48 @@ module riscv_core
dstvalue
<=
mul_result
[
63
:
32
]
;
end
4
:
begin
dstreg
<=
0
;
dstvalue
<=
0
;
if
((
rs2
==
0
))
begin
dstvalue
<=
32'hffffffff
;
end
else
begin
dstreg
<=
0
;
dstvalue
<=
0
;
end
end
5
:
begin
dstreg
<=
0
;
dstvalue
<=
0
;
if
((
rs2
==
0
))
begin
dstvalue
<=
32'hffffffff
;
end
else
begin
dstreg
<=
0
;
dstvalue
<=
0
;
end
end
6
:
begin
dstreg
<=
0
;
dstvalue
<=
0
;
if
((
rs2
==
0
))
begin
dstvalue
<=
rs1
;
end
else
begin
dstreg
<=
0
;
dstvalue
<=
0
;
end
end
7
:
begin
dstreg
<=
0
;
dstvalue
<=
0
;
if
((
rs2
==
0
))
begin
dstvalue
<=
rs1
;
end
else
begin
dstreg
<=
0
;
dstvalue
<=
0
;
end
end
endcase
...
...
@@ -484,7 +510,7 @@ module riscv_core
bReadAddr
=
pc
;
end
else
if
((
state
==
7
))
if
((
state
==
4
))
begin
if
((
opcode
==
5'h00
))
begin
...
...
@@ -527,7 +553,7 @@ endmodule
*
)
module
ram8kb
(
input
[
32'h
a
:
32'h0
]
address
,
input
[
32'h
1d
:
32'h0
]
address
,
input
[
32'h3
:
32'h0
]
byteena
,
input
clock
,
input
[
32'h1f
:
32'h0
]
data
,
...
...
@@ -600,7 +626,7 @@ module top
wire
[
32'h3
:
32'h0
]
bWriteMask
;
wire
wRead_out
;
wire
[
32'h1f
:
32'h0
]
bReadAddr_out
;
wire
[
32'h
a
:
32'h0
]
ramaddr
;
wire
[
32'h
1d
:
32'h0
]
ramaddr
;
wire
[
32'h4
:
32'h0
]
regno
;
wire
[
32'h3
:
32'h0
]
regena
;
wire
[
32'h1f
:
32'h0
]
regwrdata
;
...
...
@@ -611,15 +637,15 @@ module top
wire
[
32'h1f
:
32'h0
]
regwrdata2
;
wire
regwren2
;
wire
[
32'h1f
:
32'h0
]
regrddata2
;
assign
bReadData
=
((((
bReadAddr_out
&
32'hffffff00
)
==
32'hf0000000
))
?
(
bReadDataKey
)
:
(((((
bReadAddr_out
&
32'hff
ffc
000
)
==
32'h0
))
?
(
bReadDataRam
)
:
(
32'hffffffff
))));
assign
ramaddr
=
((
wWrite
)
?
(
bWriteAddr
[
12
:
2
]
)
:
(
bReadAddr
[
12
:
2
]
));
assign
bReadData
=
((((
bReadAddr_out
&
32'hffffff00
)
==
32'hf0000000
))
?
(
bReadDataKey
)
:
(((((
bReadAddr_out
&
32'hff
000
000
)
==
32'h0
))
?
(
bReadDataRam
)
:
(
32'hffffffff
))));
assign
ramaddr
=
((
wWrite
)
?
(
bWriteAddr
[
31
:
2
]
)
:
(
bReadAddr
[
31
:
2
]
));
hdl4se_reg
#(
32'h1
)
readcmd
(
wClk
,
wRead
,
wRead_out
);
hdl4se_reg
#(
32'h20
)
readaddr
(
wClk
,
bReadAddr
,
bReadAddr_out
);
regfile
regs
(
regno
,
regena
,
wClk
,
regwrdata
,
regwren
,
regrddata
);
regfile
regs2
(
regno2
,
regena2
,
wClk
,
regwrdata2
,
regwren2
,
regrddata2
);
ram8kb
ram
(
ramaddr
,
(
~
(
bWriteMask
)),
wClk
,
bWriteData
,
wWrite
,
bReadDataRam
ram8kb
ram
(
ramaddr
,
(
~
(
bWriteMask
)),
wClk
,
bWriteData
,
((((
bWriteAddr
&
32'hff000000
)
==
32'h0
))
?
(
wWrite
)
:
(
0
))
,
bReadDataRam
);
digitled
led
(
wClk
,
nwReset
,
wWrite
,
bWriteAddr
,
bWriteData
,
bWriteMask
,
wRead
,
bReadAddr
,
bReadDataKey
);
...
...
examples/hdl4se_riscv/verilog/riscv_sim_v3.v
浏览文件 @
809d9d8b
...
...
@@ -55,7 +55,7 @@ endmodule
softmodule
=
"hdl4se"
*
)
module
ram8kb
(
input
[
10
:
0
]
address
,
input
[
29
:
0
]
address
,
input
[
3
:
0
]
byteena
,
input
clock
,
input
[
31
:
0
]
data
,
...
...
@@ -107,11 +107,11 @@ module top(input wClk, nwReset);
assign
bReadData
=
((
bReadAddr_out
&
32'hffffff00
)
==
32'hf0000000
)
?
bReadDataKey
:
(
((
bReadAddr_out
&
32'hff
ffc
000
)
==
32'h00000000
)
?
bReadDataRam
:
(
32'hffffffff
)
((
bReadAddr_out
&
32'hff
000
000
)
==
32'h00000000
)
?
bReadDataRam
:
(
32'hffffffff
)
);
wire
[
10
:
0
]
ramaddr
;
assign
ramaddr
=
wWrite
?
bWriteAddr
[
12
:
2
]
:
bReadAddr
[
12
:
2
];
wire
[
29
:
0
]
ramaddr
;
assign
ramaddr
=
wWrite
?
bWriteAddr
[
31
:
2
]
:
bReadAddr
[
31
:
2
];
wire
[
4
:
0
]
regno
;
wire
[
3
:
0
]
regena
;
...
...
@@ -126,7 +126,7 @@ module top(input wClk, nwReset);
regfile
regs
(
regno
,
regena
,
wClk
,
regwrdata
,
regwren
,
regrddata
);
regfile
regs2
(
regno2
,
regena2
,
wClk
,
regwrdata2
,
regwren2
,
regrddata2
);
ram8kb
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
wWrite
,
bReadDataRam
);
ram8kb
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
((
bWriteAddr
&
32'hff000000
)
==
0
)
?
wWrite
:
1'b0
,
bReadDataRam
);
digitled
led
(
wClk
,
nwReset
,
wWrite
,
bWriteAddr
,
bWriteData
,
bWriteMask
,
wRead
,
bReadAddr
,
bReadDataKey
);
riscv_core
core
(
wClk
,
nwReset
,
wWrite
,
bWriteAddr
,
bWriteData
,
bWriteMask
,
wRead
,
bReadAddr
,
bReadData
,
regno
,
regena
,
regwrdata
,
regwren
,
regrddata
,
...
...
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