Merge branch 'master' into gitee_master

bsp/essemi/es8p508x/SConscript

 # RT-Thread SConscript bridge
 import os
+from building import *
 
 objs = []
-cwd  = GetCurrentDir()
+cwd = GetCurrentDir()
 list = os.listdir(cwd)
 
 for d in list:

bsp/imx6ul/SConstruct

@@ -20,6 +20,7 @@ env = Environment(tools = ['mingw'],
 	AR = rtconfig.AR, ARFLAGS = '-rc',
 	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
 
 Export('RTT_ROOT')
 Export('rtconfig')

bsp/imxrt/imxrt1052-nxp-evk/rtconfig.py

@@ -53,6 +53,9 @@ if PLATFORM == 'gcc':
     CPATH = ''
     LPATH = ''
 
+    AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
+    AFLAGS += ' -D__STARTUP_CLEAR_BSS'
+
     if BUILD == 'debug':
         CFLAGS += ' -gdwarf-2'
         AFLAGS += ' -gdwarf-2'
@@ -60,7 +63,7 @@ if PLATFORM == 'gcc':
     else:
         CFLAGS += ' -O2 -Os'
 
-    POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
 
     # module setting 
     CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '

bsp/imxrt/imxrt1064-nxp-evk/README.md

@@ -71,7 +71,7 @@
 
 ### 快速上手
 
-本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，暂不支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，以及GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
 
 #### 硬件连接
 
@@ -115,4 +115,4 @@ msh >
 
 维护人:
 
--  [王强](https://github.com/xfwangqiang), 邮箱：<164877907@qq.com>
\ No newline at end of file
+-  [王强](https://github.com/xfwangqiang, https://gitee.com/xfwangqiang), 邮箱：<164877907@qq.com>
\ No newline at end of file

bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py

@@ -53,6 +53,9 @@ if PLATFORM == 'gcc':
     CPATH = ''
     LPATH = ''
 
+    AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
+    AFLAGS += ' -D__STARTUP_CLEAR_BSS'
+
     if BUILD == 'debug':
         CFLAGS += ' -gdwarf-2'
         AFLAGS += ' -gdwarf-2'

bsp/nrf5x/libraries/drivers/SConscript

@@ -19,8 +19,12 @@ if GetDepend(['BSP_USING_QSPI_FLASH']):
 
 if GetDepend(['BSP_USING_SPI']):
     src += ['drv_spi.c']
+    
 if GetDepend(['BSP_USING_GPIO']):
     src += ['drv_gpio.c']
+    
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
 
 path =  [cwd]
 

bsp/nrf5x/libraries/drivers/drv_gpio.c

@@ -46,22 +46,6 @@ static const struct pin_index pins[] =
     __NRF5X_PIN(29,  0, 29),
     __NRF5X_PIN(30,  0, 30),
     __NRF5X_PIN(31,  0, 31),
-    __NRF5X_PIN(32,  1, 0 ),
-    __NRF5X_PIN(33,  1, 1 ),
-    __NRF5X_PIN(34,  1, 2 ),
-    __NRF5X_PIN(35,  1, 3 ),
-    __NRF5X_PIN(36,  1, 4 ),
-    __NRF5X_PIN(37,  1, 5 ),
-    __NRF5X_PIN(38,  1, 6 ),
-    __NRF5X_PIN(39,  1, 7 ),
-    __NRF5X_PIN(40,  1, 8 ),
-    __NRF5X_PIN(41,  1, 9 ),
-    __NRF5X_PIN(42,  1, 10),
-    __NRF5X_PIN(43,  1, 11),
-    __NRF5X_PIN(44,  1, 12),
-    __NRF5X_PIN(45,  1, 13),
-    __NRF5X_PIN(46,  1, 14),
-    __NRF5X_PIN(47,  1, 15),
 };
 
 /* EVENTS_IN[n](n=0..7) and EVENTS_PORT */

bsp/nrf5x/libraries/drivers/drv_gpio.h

@@ -13,7 +13,6 @@
 
 #include <board.h>
 #include <rtdevice.h>
-#include <nrf52840.h>
 #include <hal/nrf_gpio.h>
 #include <drivers/include/nrfx_gpiote.h>
 

bsp/nrf5x/libraries/drivers/drv_pwm.c

+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-26     supperthomas first version
+ *
+ */
+
+
+#include <board.h>
+#include "rtdevice.h"
+#include "rtservice.h"
+
+#ifdef RT_USING_PWM
+
+#include <nrfx_pwm.h>
+
+struct mcu_pwm
+{
+    struct rt_device_pwm pwm_device;
+    
+    nrfx_pwm_t *pwm_handle;
+    nrf_pwm_values_individual_t m_demo1_seq_values;
+    nrf_pwm_sequence_t m_demo1_seq;
+
+    rt_uint8_t channel;
+    char *name;
+    rt_uint64_t pwm_src_clk;
+    uint8_t channel_0_pin;
+    uint8_t channel_1_pin;
+    uint8_t channel_2_pin;
+    uint8_t channel_3_pin;
+};
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    PWM3_INDEX,
+#endif
+};
+#ifdef BSP_USING_PWM0
+static nrfx_pwm_t m_pwm0 = NRFX_PWM_INSTANCE(0);
+#define PWM0_CONFIG                             \
+    {                                           \
+       .pwm_handle              =  &m_pwm0,     \
+       .name                    = "pwm0",       \
+       .pwm_src_clk             = 1000000,      \
+    }
+#endif
+
+#ifdef BSP_USING_PWM1
+static nrfx_pwm_t m_pwm1 = NRFX_PWM_INSTANCE(1);
+#define PWM1_CONFIG                             \
+    {                                           \
+       .pwm_handle              =  &m_pwm1,         \
+       .name                    = "pwm1",       \
+       .pwm_src_clk             = 1000000,             \
+    }
+#endif
+
+#ifdef BSP_USING_PWM2
+static nrfx_pwm_t m_pwm2 = NRFX_PWM_INSTANCE(2);
+#define PWM2_CONFIG                             \
+    {                                           \
+       .pwm_handle              =  &m_pwm2,         \
+       .name                    = "pwm2",       \
+       .pwm_src_clk             = 1000000,             \
+    }
+#endif
+
+#ifdef BSP_USING_PWM3
+static nrfx_pwm_t m_pwm3 = NRFX_PWM_INSTANCE(3);
+#define PWM3_CONFIG                             \
+    {                                           \
+       .pwm_handle              =  &m_pwm3,         \
+       .name                    = "pwm3",       \
+       .pwm_src_clk             = 1000000,             \
+    }
+#endif
+
+static struct mcu_pwm mcu_pwm_obj[] =
+{
+#ifdef BSP_USING_PWM0
+    PWM0_CONFIG,
+#endif
+#ifdef BSP_USING_PWM1
+    PWM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM2
+    PWM2_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM3
+    PWM3_CONFIG,
+#endif
+};
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+static struct rt_pwm_ops drv_ops =
+{
+    drv_pwm_control
+};
+
+static rt_err_t drv_pwm_enable(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    if (!enable)
+    {
+        nrfx_pwm_stop(p_mcu->pwm_handle, true);
+    }
+    else
+    {
+        (void)nrfx_pwm_simple_playback(p_mcu->pwm_handle, &p_mcu->m_demo1_seq, 1, NRFX_PWM_FLAG_LOOP);
+    }
+
+    return RT_EOK;
+}
+
+uint8_t mcu_get_channel_number(uint8_t channel)
+{
+    if (channel & 0x01)
+    {
+        return 0;
+    }
+    else if (channel & 0x02)
+    {
+        return 1;
+    }
+    else if (channel & 0x04)
+    {
+        return 2;
+    }
+    else if (channel & 0x08)
+    {
+        return 3;
+    }
+    return 0;
+}
+
+static rt_err_t drv_pwm_get(struct mcu_pwm *pwm_handle, struct rt_pwm_configuration *configuration)
+{
+    rt_uint8_t channel_number = mcu_get_channel_number(configuration->channel);
+    uint8_t tick_pscond;
+
+    tick_pscond = pwm_handle->pwm_src_clk / 1000000UL;
+    configuration->period = pwm_handle->pwm_handle->p_registers->COUNTERTOP * 1000UL / tick_pscond;
+    configuration->pulse = pwm_handle->pwm_handle->p_registers->SEQ[channel_number].PTR / tick_pscond;
+
+    return RT_EOK;
+}
+
+static void nrfx_set_prioid(nrfx_pwm_t *pwm_handle, uint32_t perioid)
+{
+    pwm_handle->p_registers->COUNTERTOP = perioid;
+}
+
+static rt_err_t drv_pwm_set(struct mcu_pwm *p_mcu, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t period, pulse;
+    uint8_t tick_pscond;
+    tick_pscond = p_mcu->pwm_src_clk / 1000000UL;
+
+    p_mcu->pwm_handle->p_registers->COUNTERTOP = (unsigned long long)configuration->period * tick_pscond;
+    if (configuration->channel & 0x01)
+    {
+        p_mcu->m_demo1_seq_values.channel_0 = configuration->pulse;
+    }
+
+    if (configuration->channel & 0x02)
+    {
+        p_mcu->m_demo1_seq_values.channel_1 = configuration->pulse;
+    }
+
+    if (configuration->channel & 0x04)
+    {
+        p_mcu->m_demo1_seq_values.channel_2 = configuration->pulse;
+    }
+
+    if (configuration->channel & 0x08)
+    {
+        p_mcu->m_demo1_seq_values.channel_3 = configuration->pulse;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    void *pwm_handle = (void *)device->parent.user_data;
+    nrfx_pwm_t *p_handle = (nrfx_pwm_t *)pwm_handle;
+    struct mcu_pwm *p_mcu = rt_container_of(p_handle, struct mcu_pwm, pwm_handle);
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(p_mcu, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(p_mcu, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return drv_pwm_set(p_mcu, configuration);
+    case PWM_CMD_GET:
+        return drv_pwm_get(p_mcu, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+static rt_err_t mcu_hw_pwm_init(struct mcu_pwm *device)
+{
+#define NRFX_PWM_PIN_INVERTED    0x80
+#define _PRIO_APP_LOWEST    7
+    nrfx_pwm_config_t config0 =
+    {
+        .irq_priority = _PRIO_APP_LOWEST,
+        .base_clock   = NRF_PWM_CLK_1MHz,  //default value
+        .count_mode   = NRF_PWM_MODE_UP,
+        .top_value    = 5000,              //default vaule
+        .load_mode    = NRF_PWM_LOAD_INDIVIDUAL,
+        .step_mode    = NRF_PWM_STEP_AUTO
+    };
+    rt_err_t result = RT_EOK;
+    if (device->pwm_src_clk == 1000000)
+    {
+        config0.base_clock = NRF_PWM_CLK_1MHz;
+    }
+    else if (device->pwm_src_clk == 2000000)
+    {
+        config0.base_clock = NRF_PWM_CLK_2MHz;
+    }
+    else if (device->pwm_src_clk == 8000000)
+    {
+        config0.base_clock = NRF_PWM_CLK_8MHz;
+    }
+    else
+    {
+        config0.base_clock = NRF_PWM_CLK_1MHz;
+    }
+
+    if (device->channel & 0x01)
+    {
+        config0.output_pins[0] = device->channel_0_pin | NRFX_PWM_PIN_INVERTED;
+    }
+
+    if (device->channel & 0x02)
+    {
+        config0.output_pins[1] = device->channel_1_pin | NRFX_PWM_PIN_INVERTED;
+    }
+
+    if (device->channel & 0x04)
+    {
+        config0.output_pins[2] = device->channel_2_pin | NRFX_PWM_PIN_INVERTED;
+    }
+
+    if (device->channel & 0x08)
+    {
+        config0.output_pins[3] = device->channel_3_pin | NRFX_PWM_PIN_INVERTED;
+    }
+    device->m_demo1_seq.values.p_individual = &device->m_demo1_seq_values;
+    device->m_demo1_seq.length = NRF_PWM_VALUES_LENGTH(device->m_demo1_seq_values),
+                        nrfx_pwm_init(device->pwm_handle, &config0, NULL, NULL);
+    return result;
+}
+
+static void pwm_get_channel(void)
+{
+#ifdef BSP_USING_PWM0_CH0
+    mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 0;
+    mcu_pwm_obj[PWM0_INDEX].channel_0_pin = BSP_USING_PWM0_CH0;
+#endif
+#ifdef BSP_USING_PWM0_CH1
+    mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 1;
+    mcu_pwm_obj[PWM0_INDEX].channel_1_pin = BSP_USING_PWM0_CH1;
+#endif
+#ifdef BSP_USING_PWM0_CH2
+    mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 2;
+    mcu_pwm_obj[PWM0_INDEX].channel_2_pin = BSP_USING_PWM0_CH2;
+#endif
+#ifdef BSP_USING_PWM0_CH3
+    mcu_pwm_obj[PWM0_INDEX].channel |= 1 << 3;
+    mcu_pwm_obj[PWM0_INDEX].channel_3_pin = BSP_USING_PWM0_CH3;
+#endif
+#ifdef BSP_USING_PWM1_CH0
+    mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
+    mcu_pwm_obj[PWM1_INDEX].channel_0_pin = BSP_USING_PWM1_CH0;
+#endif
+#ifdef BSP_USING_PWM1_CH1
+    mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
+    mcu_pwm_obj[PWM1_INDEX].channel_1_pin = BSP_USING_PWM1_CH1;
+#endif
+#ifdef BSP_USING_PWM1_CH2
+    mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
+    mcu_pwm_obj[PWM1_INDEX].channel_2_pin = BSP_USING_PWM1_CH2;
+#endif
+#ifdef BSP_USING_PWM1_CH3
+    mcu_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
+    mcu_pwm_obj[PWM1_INDEX].channel_3_pin = BSP_USING_PWM1_CH3;
+#endif
+#ifdef BSP_USING_PWM2_CH0
+    mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
+    mcu_pwm_obj[PWM2_INDEX].channel_0_pin = BSP_USING_PWM2_CH0;
+#endif
+#ifdef BSP_USING_PWM2_CH1
+    mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
+    mcu_pwm_obj[PWM2_INDEX].channel_1_pin = BSP_USING_PWM2_CH1;
+#endif
+#ifdef BSP_USING_PWM2_CH2
+    mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
+    mcu_pwm_obj[PWM2_INDEX].channel_2_pin = BSP_USING_PWM2_CH2;
+#endif
+#ifdef BSP_USING_PWM2_CH3
+    mcu_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
+    mcu_pwm_obj[PWM2_INDEX].channel_3_pin = BSP_USING_PWM2_CH3;
+#endif
+#ifdef BSP_USING_PWM3_CH0
+    mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
+    mcu_pwm_obj[PWM3_INDEX].channel_0_pin = BSP_USING_PWM3_CH0;
+#endif
+#ifdef BSP_USING_PWM3_CH1
+    mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
+    mcu_pwm_obj[PWM3_INDEX].channel_1_pin = BSP_USING_PWM3_CH1;
+#endif
+#ifdef BSP_USING_PWM3_CH2
+    mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
+    mcu_pwm_obj[PWM3_INDEX].channel_2_pin = BSP_USING_PWM3_CH2;
+#endif
+#ifdef BSP_USING_PWM3_CH3
+    mcu_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
+    mcu_pwm_obj[PWM3_INDEX].channel_3_pin = BSP_USING_PWM3_CH3;
+#endif
+}
+
+static int mcu_pwm_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    pwm_get_channel();
+    for (i = 0; i < sizeof(mcu_pwm_obj) / sizeof(mcu_pwm_obj[0]); i++)
+    {
+        /* pwm init */
+        if (mcu_hw_pwm_init(&mcu_pwm_obj[i]) != RT_EOK)
+        {
+            rt_kprintf("\r\n %s init failed", mcu_pwm_obj[i].name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+        else
+        {
+            rt_kprintf("\r\n %s init success", mcu_pwm_obj[i].name);
+
+            /* register pwm device */
+            if (rt_device_pwm_register(&mcu_pwm_obj[i].pwm_device, mcu_pwm_obj[i].name, &drv_ops, &mcu_pwm_obj[i].pwm_handle) == RT_EOK)
+            {
+                rt_kprintf("\r\n %s register success", mcu_pwm_obj[i].name);
+            }
+            else
+            {
+                rt_kprintf("\r\n %s register failed", mcu_pwm_obj[i].name);
+                result = -RT_ERROR;
+            }
+        }
+    }
+__exit:
+    return result;
+}
+INIT_DEVICE_EXPORT(mcu_pwm_init);
+
+
+
+/* test example */
+#define PWM_DEV_NAME        "pwm0"  /* PWM  name*/
+#define PWM_DEV_CHANNEL     15       /* PWM  channel */
+
+struct rt_device_pwm *pwm_dev;
+
+static int pwm_led_sample(int argc, char *argv[])
+{
+    rt_uint32_t period, pulse, dir;
+
+    period = 50000;   /* 50ms*/
+    dir = 1;
+    pulse = 0;
+
+
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+
+    while (1)
+    {
+        rt_thread_mdelay(50);
+        if (dir)
+        {
+            pulse += 500;
+        }
+        else
+        {
+            pulse -= 500;
+        }
+        if (pulse >= period)
+        {
+            dir = 0;
+        }
+        if (0 == pulse)
+        {
+            dir = 1;
+        }
+
+
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    }
+}
+MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
+
+#endif
\ No newline at end of file

bsp/nrf5x/nrf52832/.config

@@ -74,7 +74,9 @@ CONFIG_RT_VER_NUM=0x40003
 # RT-Thread Components
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
-# CONFIG_RT_USING_USER_MAIN is not set
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
 
 #
 # C++ features
@@ -112,7 +114,7 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
@@ -120,6 +122,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_I2C is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
@@ -192,12 +195,15 @@ CONFIG_RT_USING_LIBC=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -224,6 +230,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -236,9 +243,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -257,6 +265,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
 
 #
 # security packages
@@ -265,6 +274,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -299,6 +309,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
 
 #
 # system packages
@@ -309,6 +321,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -321,6 +334,9 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -338,6 +354,13 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+CONFIG_PKG_USING_NRFX=y
+CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
+CONFIG_PKG_USING_NRFX_V210=y
+# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set
+CONFIG_PKG_NRFX_VER="v2.1.0"
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -355,13 +378,19 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
 # CONFIG_PKG_USING_MAX7219 is not set
 # CONFIG_PKG_USING_BEEP is not set
-# CONFIG_PKG_USING_NORDIC_SDK is not set
-# CONFIG_PKG_USING_NORDIC_SDK_V100 is not set
-# CONFIG_PKG_USING_NORDIC_SDK_LATEST_VERSION is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
 
 #
 # miscellaneous packages
@@ -398,17 +427,39 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
 
 #
 # Hardware Drivers Config
 #
 CONFIG_SOC_NRF52832=y
+CONFIG_SOC_NORDIC=y
 
 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_JLINK_TO_USART is not set
+# CONFIG_BSP_USING_QSPI_FLASH is not set
 
 #
 # On-chip Peripheral Drivers
 #
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_SOFTDEVICE is not set
 CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+CONFIG_BSP_UART0_RX_PIN=8
+CONFIG_BSP_UART0_TX_PIN=6
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+
+#
+# On-chip flash config
+#
+CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
+CONFIG_MCU_FLASH_SIZE_KB=1024
+CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
+CONFIG_MCU_SRAM_SIZE_KB=256
+CONFIG_MCU_FLASH_PAGE_SIZE=0x1000

bsp/nrf5x/nrf52832/SConstruct

@@ -50,5 +50,8 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
 
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)

bsp/nrf5x/nrf52832/applications/application.c

 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-/**
- * @addtogroup NRF52832
+ * 2020-04-29     supperthomas first version
+ *
  */
-/*@{*/
 
 #include <rtthread.h>
+#include <rtdevice.h>
+#define DK_BOARD_LED_1  17
+#define DK_BOARD_LED_2  18
 
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#include <shell.h>
-#endif
-
-void rt_init_thread_entry(void* parameter)
+int main(void)
 {
-    extern rt_err_t ble_init(void);
-
-    ble_init();
+    int count = 1; 
+    rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
+    
+    while (count++)
+    {    
+        rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
+        rt_thread_mdelay(500);
+        
+        rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
+        rt_thread_mdelay(500);                    
+    }
+    return RT_EOK;
 }
 
-int rt_application_init(void)
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024,
-                            RT_THREAD_PRIORITY_MAX / 3, 20);
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
-    return 0;
-}
-
-
-/*@}*/

bsp/nrf5x/nrf52832/applications/startup.c

-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-/**
- * @addtogroup NRF52832
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define NRF_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define NRF_SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define NRF_SRAM_BEGIN    (&__bss_end)
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init tick */
-    rt_system_tick_init();
-
-    /* init kernel object */
-    rt_system_object_init();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)NRF_SRAM_BEGIN, (void*)CHIP_SRAM_END);
-#endif
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_init();
-#endif
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int main(void)
-{
-    /* disable interrupt first */
-    // rt_hw_interrupt_disable();
-
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    return 0;
-}
-
-/*@}*/

bsp/nrf5x/nrf52832/board/Kconfig

@@ -2,21 +2,293 @@ menu "Hardware Drivers Config"
 
 config SOC_NRF52832
     bool
+    config SOC_NRF52832
     select RT_USING_COMPONENTS_INIT
-    # select RT_USING_USER_MAIN
+    select RT_USING_USER_MAIN
+    default y
+
+config SOC_NORDIC
+    bool 
+    config SOC_NORDIC
     default y
 
-menu "Onboard Peripheral Drivers"
 
+menu "Onboard Peripheral Drivers"
+    config BSP_USING_JLINK_TO_USART
+        bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
+        select BSP_USING_UART
+        select BSP_USING_UART0
+        default y
 endmenu
 
 menu "On-chip Peripheral Drivers"
-
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        select RT_USING_PWM
+        default n
+        if BSP_USING_PWM
+                config NRFX_PWM_ENABLED
+                int 
+                default 1
+                config BSP_USING_PWM0
+                    bool "Enable PWM0 bus"
+                    default y
+                if BSP_USING_PWM0
+                    config NRFX_PWM0_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM0_CH0
+                        int "PWM0 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM0_CH1
+                        int "PWM0 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM0_CH2
+                        int "PWM0 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM0_CH3
+                        int "PWM0 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM1
+                    bool "Enable PWM1 bus"
+                    default n
+                if BSP_USING_PWM1
+                    config NRFX_PWM1_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM1_CH0
+                        int "PWM1 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM1_CH1
+                        int "PWM1 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM1_CH2
+                        int "PWM1 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM1_CH3
+                        int "PWM1 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM2
+                    bool "Enable PWM2 bus"
+                    default n
+                if BSP_USING_PWM2
+                    config NRFX_PWM2_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM2_CH0
+                        int "PWM2 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM2_CH1
+                        int "PWM2 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM2_CH2
+                        int "PWM2 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM2_CH3
+                        int "PWM2 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM3
+                    bool "Enable PWM3 bus"
+                    default n
+                if BSP_USING_PWM3
+                    config NRFX_PWM3_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM3_CH0
+                        int "PWM3 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM3_CH1
+                        int "PWM3 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM3_CH2
+                        int "PWM3 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM3_CH3
+                        int "PWM3 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+        endif
+    menuconfig BSP_USING_SOFTDEVICE
+        bool "Enable NRF SOFTDEVICE"
+        select PKG_USING_NRF5X_SDK
+        select NRFX_CLOCK_ENABLED
+        default n
+if BSP_USING_SOFTDEVICE
+    config NRFX_CLOCK_ENABLED
+    int 
+    default 1
+    config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+    int 
+    default 7
+    config NRFX_RTC_ENABLED
+    int 
+    default 1
+    config NRFX_RTC1_ENABLED
+    int 
+    default 1
+    config NRF_CLOCK_ENABLED
+    int 
+    default 1
+    config NRF_SDH_BLE_ENABLED
+    int 
+    default 1
+    config NRF_SDH_ENABLED
+    int 
+    default 1
+    config NRF_SDH_SOC_ENABLED
+    int 
+    default 1
+endif
     menuconfig BSP_USING_UART
         bool "Enable UART"
         default y
         select RT_USING_SERIAL
 
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y 
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_PIN
+                        int "uart0 rx pin number"
+                        range 0 31
+                        default 8
+                    config BSP_UART0_TX_PIN
+                        int "uart0 tx pin number"
+                        range 0 31
+                        default 6
+                endif
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+        endif
+
+    config BSP_USING_SPI
+        bool "Enable SPI"
+        select RT_USING_PIN
+        default y
+
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0 bus"
+                default y
+            if BSP_USING_SPI0
+                config BSP_SPI0_SCK_PIN
+                    int "SPI0 sck pin number set"
+                    range 0 47
+                    default 28
+                config BSP_SPI0_MOSI_PIN
+                    int "SPI0 mosi pin number set"
+                    range 0 47
+                    default 29
+                config BSP_SPI0_MISO_PIN
+                    int "SPI0 miso pin number set"
+                    range 0 47
+                    default 30
+                config BSP_SPI0_SS_PIN
+                    int "SPI0 ss pin number set"
+                    range 0 47
+                    default 31
+            endif
+
+            config BSP_USING_SPI1
+                bool "Enable SPI1 bus"
+                default n
+            if BSP_USING_SPI1
+                config BSP_SPI1_SCK_PIN
+                    int "SPI0 sck pin number set"
+                    range 0 47
+                    default 28
+                config BSP_SPI1_MOSI_PIN
+                    int "SPI0 mosi pin number set"
+                    range 0 47
+                    default 29
+                config BSP_SPI1_MISO_PIN
+                    int "SPI0 miso pin number set"
+                    range 0 47
+                    default 30
+                config BSP_SPI1_SS_PIN
+                    int "SPI0 ss pin number set"
+                    range 0 47
+                    default 31
+            endif
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2 bus"
+                default n
+            if BSP_USING_SPI2
+                config BSP_SPI2_SCK_PIN
+                    int "SPI0 sck pin number set"
+                    range 0 47
+                    default 28
+                config BSP_SPI2_MOSI_PIN
+                    int "SPI0 mosi pin number set"
+                    range 0 47
+                    default 29
+                config BSP_SPI2_MISO_PIN
+                    int "SPI0 miso pin number set"
+                    range 0 47
+                    default 30
+                config BSP_SPI2_SS_PIN
+                    int "SPI0 ss pin number set"
+                    range 0 47
+                    default 31
+            endif
+
+        endif
+    config BSP_USING_ON_CHIP_FLASH
+        select PKG_USING_FAL
+        bool "Enable on-chip FLASH"
+        default n
+
+    menu "On-chip flash config"
+
+        config MCU_FLASH_START_ADDRESS  
+            hex "MCU FLASH START ADDRESS"
+            default 0x00000000
+
+        config MCU_FLASH_SIZE_KB  
+            int "MCU FLASH SIZE, MAX size 1024 KB"
+            range 1 1024
+            default 1024		
+
+        config MCU_SRAM_START_ADDRESS 
+            hex "MCU RAM START ADDRESS"
+            default 0x20000000
+
+        config MCU_SRAM_SIZE_KB 
+            int "MCU RAM SIZE, MAX size 256 KB"
+            range 1 256
+            default 256
+
+        config MCU_FLASH_PAGE_SIZE 
+            hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
+            range 0x1000 0x1000
+            default 0x1000
+	endmenu
 endmenu
 
 endmenu

bsp/nrf5x/nrf52832/board/SConscript

@@ -5,6 +5,7 @@ from building import *
 cwd = GetCurrentDir()
 src = Glob('*.c')
 CPPPATH = [cwd]
+define = ['USE_APP_CONFIG']
 
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,)
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define)
 Return('group')

bsp/nrf5x/nrf52832/board/app_config.h

+#ifndef APP_CONFIG_H
+#define APP_CONFIG_H
+
+#endif	//APP_CONFIG_H

bsp/nrf5x/nrf52832/board/board.c

-#include "board.h"
-#include "drv_uart.h"
-#include "app_util_platform.h"
-#include "nrf_drv_common.h"
-#include "nrf_systick.h"
-#include "nrf_rtc.h"
-#include "nrf_drv_clock.h"
-#include "softdevice_handler.h"
-#include "nrf_drv_uart.h"
-#include "nrf_gpio.h"
-
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
 #include <rtthread.h>
 #include <rthw.h>
+#include <nrfx_systick.h>
 
-#define TICK_RATE_HZ  RT_TICK_PER_SECOND
-#define SYSTICK_CLOCK_HZ  ( 32768UL )
-
-#define NRF_RTC_REG        NRF_RTC1
-    /* IRQn used by the selected RTC */
-#define NRF_RTC_IRQn       RTC1_IRQn
-    /* Constants required to manipulate the NVIC. */
-#define NRF_RTC_PRESCALER  ( (uint32_t) (ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
-    /* Maximum RTC ticks */
-#define NRF_RTC_MAXTICKS   ((1U<<24)-1U)
-
-static volatile uint32_t m_tick_overflow_count = 0;
-#define NRF_RTC_BITWIDTH 24
-#define OSTick_Handler     RTC1_IRQHandler
-#define EXPECTED_IDLE_TIME_BEFORE_SLEEP   2
-
-void SysTick_Configuration(void)
-{
-    nrf_drv_clock_lfclk_request(NULL);
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    nrf_rtc_prescaler_set(NRF_RTC_REG, NRF_RTC_PRESCALER);
-    nrf_rtc_int_enable   (NRF_RTC_REG, RTC_INTENSET_TICK_Msk);
-    nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_CLEAR);
-    nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_START);
-    nrf_rtc_event_enable(NRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk);
-
-    NVIC_SetPriority(NRF_RTC_IRQn, 0xF);
-    NVIC_EnableIRQ(NRF_RTC_IRQn);
-}
+#include "board.h"
+#include "drv_uart.h"
+#ifdef BSP_USING_SOFTDEVICE
+#include <nrfx_rtc.h>
+#include <nrfx_clock.h>
+#include "app_error.h"
+#include "nrf_drv_clock.h"
+const nrfx_rtc_t rtc = NRFX_RTC_INSTANCE(1); /**< Declaring an instance of nrf_drv_rtc for RTC0. */
 
-static rt_tick_t _tick_distance(void)
+static void rtc_handler(nrfx_rtc_int_type_t int_type)
 {
-    nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
+    if (int_type == NRFX_RTC_INT_TICK)
+    {
+        rt_interrupt_enter();
 
-    uint32_t systick_counter = nrf_rtc_counter_get(NRF_RTC_REG);
-    nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
+        rt_tick_increase();
 
-    /* check for overflow in TICK counter */
-    if(nrf_rtc_event_pending(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW))
-    {
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW);
-        m_tick_overflow_count++;
+        rt_interrupt_leave();
     }
-
-    return ((m_tick_overflow_count << NRF_RTC_BITWIDTH) + systick_counter) - rt_tick_get();
 }
-
-void OSTick_Handler( void )
+#else
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
 {
-    uint32_t diff;
-
-	/* enter interrupt */
+    /* enter interrupt */
     rt_interrupt_enter();
-    diff = _tick_distance();
 
-    while((diff--) > 0)
-    {
-        if (rt_thread_self() != RT_NULL)
-        {
-          rt_tick_increase();
-        }
-    }
+    rt_tick_increase();
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
-
-static void _wakeup_tick_adjust(void)
-{
-    uint32_t diff;
-    uint32_t level;
-
-    level = rt_hw_interrupt_disable();
-
-    diff = _tick_distance();
-
-    rt_tick_set(rt_tick_get() + diff);
-
-    if (rt_thread_self() != RT_NULL)
-    {
-    	struct rt_thread *thread;
-
-        /* check time slice */
-        thread = rt_thread_self();
-
-        if (thread->remaining_tick <= diff)
-        {
-            /* change to initialized tick */
-            thread->remaining_tick = thread->init_tick;
-
-            /* yield */
-            rt_thread_yield();
-        }
-        else
-        {
-            thread->remaining_tick -= diff;
-        }
-
-        /* check timer */
-        rt_timer_check();
-    }
-
-    rt_hw_interrupt_enable(level);
-}
-
-static void _sleep_ongo( uint32_t sleep_tick )
+#endif
+void SysTick_Configuration(void)
 {
-    uint32_t enterTime;
-    uint32_t entry_tick;
-
-    /* Make sure the SysTick reload value does not overflow the counter. */
-    if ( sleep_tick > NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP )
-    {
-        sleep_tick = NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP;
-    }
-
-    rt_enter_critical();
-
-    enterTime = nrf_rtc_counter_get(NRF_RTC_REG);
-
-    {
-        uint32_t wakeupTime = (enterTime + sleep_tick) & NRF_RTC_MAXTICKS;
-
-        /* Stop tick events */
-        nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-
-        /* Configure CTC interrupt */
-        nrf_rtc_cc_set(NRF_RTC_REG, 0, wakeupTime);
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-        nrf_rtc_int_enable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
+#ifdef BSP_USING_SOFTDEVICE
+    nrf_drv_clock_init();
+    nrf_drv_clock_lfclk_request(NULL);
 
-        entry_tick = rt_tick_get();
+    uint32_t err_code;
+#define TICK_RATE_HZ  RT_TICK_PER_SECOND
+#define SYSTICK_CLOCK_HZ  ( 32768UL )
 
-        __DSB();
+#define NRF_RTC_REG        NRF_RTC1
+    /* IRQn used by the selected RTC */
+#define NRF_RTC_IRQn       RTC1_IRQn
+    /* Constants required to manipulate the NVIC. */
+#define NRF_RTC_PRESCALER  ( (uint32_t) (NRFX_ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
+    nrfx_rtc_config_t config = NRFX_RTC_DEFAULT_CONFIG;
+    config.prescaler = NRF_RTC_PRESCALER;
+
+    err_code = nrfx_rtc_init(&rtc, &config, rtc_handler);
+    // APP_ERROR_CHECK(err_code);
+    nrfx_rtc_tick_enable(&rtc, true);
+#define COMPARE_COUNTERTIME  (3UL)                                        /**< Get Compare event COMPARE_TIME seconds after the counter starts from 0. */
+    //Set compare channel to trigger interrupt after COMPARE_COUNTERTIME seconds
+    err_code = nrfx_rtc_cc_set(&rtc, 0, COMPARE_COUNTERTIME * 8, true);
+    // APP_ERROR_CHECK(err_code);
+
+    //Power on RTC instance
+    nrfx_rtc_enable(&rtc);
+#else
+    /* Set interrupt priority */
+    NVIC_SetPriority(SysTick_IRQn, 0xf);
 
-        if ( sleep_tick > 0 )
-        {
-#ifdef SOFTDEVICE_PRESENT
-            if (softdevice_handler_is_enabled())
-            {
-                uint32_t err_code = sd_app_evt_wait();
-                APP_ERROR_CHECK(err_code);
-            }
-            else
+    /* Configure SysTick to interrupt at the requested rate. */
+    nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
+    nrf_systick_val_clear();
+    nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
+                        | NRF_SYSTICK_CSR_ENABLE);
 #endif
-            {
-                /* No SD -  we would just block interrupts globally.
-                * BASEPRI cannot be used for that because it would prevent WFE from wake up.
-                */
-                do{
-                    __WFE();
-                } while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1]));
-            }
-        }
-
-        nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-
-        _wakeup_tick_adjust();
-
-        /* Correct the system ticks */
-        {
-
-            nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
-            nrf_rtc_int_enable (NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-            /* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */
-            NVIC_ClearPendingIRQ(NRF_RTC_IRQn);
-        }
-
-        // rt_kprintf("entry tick:%u, expected:%u, current tick:%u\n", entry_tick, sleep_tick, rt_tick_get());
-    }
-
-    rt_exit_critical();
 }
 
 
-void rt_hw_system_powersave(void)
-{
-    uint32_t sleep_tick;
-
-    sleep_tick = rt_timer_next_timeout_tick() - rt_tick_get();
-
-    if ( sleep_tick >= EXPECTED_IDLE_TIME_BEFORE_SLEEP)
-    {
-        // rt_kprintf("sleep entry:%u\n", rt_tick_get());
-        _sleep_ongo( sleep_tick );
-    }
-}
-
 void rt_hw_board_init(void)
 {
+    rt_hw_interrupt_enable(0);
     // sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
     /* Activate deep sleep mode */
     SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 
-    nrf_drv_clock_init();
-    // nrf_drv_clock_hfclk_request(0);
-
     SysTick_Configuration();
 
-    rt_thread_idle_sethook(rt_hw_system_powersave);
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
 
+#ifdef RT_USING_SERIAL
     rt_hw_uart_init();
+#endif
 
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
@@ -223,5 +113,20 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
+
+#ifdef BSP_USING_SOFTDEVICE
+    extern uint32_t  Image$$RW_IRAM1$$Base;
+    uint32_t const *const m_ram_start  = &Image$$RW_IRAM1$$Base;
+    if ((uint32_t)m_ram_start == 0x20000000)
+    {
+        rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
+        while (1);
+    }
+    else
+    {
+        rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
+    }
+#endif
+
 }
 

bsp/nrf5x/nrf52832/board/board.h

@@ -2,10 +2,26 @@
 #define _BOARD_H_
 
 #include <rtthread.h>
-
+#include <rthw.h>
 #include "nrf.h"
 
-#define CHIP_SRAM_END       (0x20000000 + 64*1024)
+#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
+#define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
+#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
+#define MCU_SRAM_END_ADDRESS        (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END       (0x20000000 + 64*1024)
 
 void rt_hw_board_init(void);
 

bsp/nrf5x/nrf52832/board/linker_scripts/link.sct

@@ -2,13 +2,13 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x0001F000 0x00061000  {    ; load region size_region
-  ER_IROM1 0x0001F000 0x00061000  {  ; load address = execution address
+LR_IROM1 0x00000000 0x100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x200025F8 0x0000DA08  {  ; RW data
+  RW_IRAM1 0x20000000 0x40000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }

bsp/nrf5x/nrf52832/board/nrfx_config.h

+/**
+ * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+// TODO - temporary redirection
+#include <sdk_config.h>
+
+#endif // NRFX_CONFIG_H__

bsp/nrf5x/nrf52832/board/nrfx_glue.h

+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_GLUE_H__
+#define NRFX_GLUE_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdbool.h>
+#include "nrf.h"
+/**
+ * @defgroup nrfx_glue nrfx_glue.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+// Uncomment this line to use the standard MDK way of binding IRQ handlers
+// at linking time.
+#include <soc/nrfx_irqs.h>
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for placing a runtime assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_ASSERT(expression)
+
+/**
+ * @brief Macro for placing a compile time assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_STATIC_ASSERT(expression)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for setting the priority of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ * @param priority   Priority to be set.
+ */
+#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)     NVIC_SetPriority(irq_number, priority)
+
+/**
+ * @brief Macro for enabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_ENABLE(irq_number)     NVIC_EnableIRQ(irq_number)
+
+/**
+ * @brief Macro for checking if a specific IRQ is enabled.
+ *
+ * @param irq_number IRQ number.
+ *
+ * @retval true  If the IRQ is enabled.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
+static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
+{
+    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
+}
+
+
+/**
+ * @brief Macro for disabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
+static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
+{
+    NVIC_DisableIRQ(irq_number);
+}
+
+
+/**
+ * @brief Macro for setting a specific IRQ as pending.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_SET(irq_number)
+
+/**
+ * @brief Macro for clearing the pending status of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_CLEAR(irq_number)
+
+/**
+ * @brief Macro for checking the pending status of a specific IRQ.
+ *
+ * @retval true  If the IRQ is pending.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_PENDING(irq_number)
+
+/** @brief Macro for entering into a critical section. */
+#define NRFX_CRITICAL_SECTION_ENTER()
+
+/** @brief Macro for exiting from a critical section. */
+#define NRFX_CRITICAL_SECTION_EXIT()
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that
+ *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
+ *        A compilation error is generated if the DWT unit is not present
+ *        in the SoC used.
+ */
+#define NRFX_DELAY_DWT_BASED    0
+
+/**
+ * @brief Macro for delaying the code execution for at least the specified time.
+ *
+ * @param us_time Number of microseconds to wait.
+ */
+#define NRFX_DELAY_US(us_time)
+
+//------------------------------------------------------------------------------
+
+/** @brief Atomic 32-bit unsigned type. */
+#define nrfx_atomic_t
+
+/**
+ * @brief Macro for storing a value to an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value to store.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the OR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise AND operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the AND operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise XOR operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the XOR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
+
+/**
+ * @brief Macro for running an addition operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the ADD operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
+
+/**
+ * @brief Macro for running a subtraction operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the SUB operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that the
+ *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
+ *        in a customized way and the default definitions from @c <nrfx_error.h>
+ *        should not be used.
+ */
+#define NRFX_CUSTOM_ERROR_CODES 0
+
+//------------------------------------------------------------------------------
+
+/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
+#define NRFX_EGUS_USED          0
+
+/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
+#define NRFX_TIMERS_USED        0
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_GLUE_H__

bsp/nrf5x/nrf52832/board/nrfx_log.h

+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_LOG_H__
+#define NRFX_LOG_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_log nrfx_log.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+/**
+ * @brief Macro for logging a message with the severity level ERROR.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_ERROR(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level WARNING.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_WARNING(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level INFO.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_INFO(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level DEBUG.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_DEBUG(format, ...)
+
+
+/**
+ * @brief Macro for logging a memory dump with the severity level ERROR.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level WARNING.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level INFO.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level DEBUG.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
+
+
+/**
+ * @brief Macro for getting the textual representation of a given error code.
+ *
+ * @param[in] error_code Error code.
+ *
+ * @return String containing the textual representation of the error code.
+ */
+#define NRFX_LOG_ERROR_STRING_GET(error_code)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_LOG_H__

bsp/nrf5x/nrf52832/rtconfig.h

@@ -46,6 +46,9 @@
 /* RT-Thread Components */
 
 #define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
 
 /* C++ features */
 
@@ -74,7 +77,6 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 
@@ -138,6 +140,8 @@
 
 /* peripheral libraries and drivers */
 
+#define PKG_USING_NRFX
+#define PKG_USING_NRFX_V210
 
 /* miscellaneous packages */
 
@@ -148,11 +152,25 @@
 /* Hardware Drivers Config */
 
 #define SOC_NRF52832
+#define SOC_NORDIC
 
 /* Onboard Peripheral Drivers */
 
+
 /* On-chip Peripheral Drivers */
 
+#define BSP_USING_GPIO
 #define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_PIN 8
+#define BSP_UART0_TX_PIN 6
+
+/* On-chip flash config */
+
+#define MCU_FLASH_START_ADDRESS 0x00000000
+#define MCU_FLASH_SIZE_KB 1024
+#define MCU_SRAM_START_ADDRESS 0x20000000
+#define MCU_SRAM_SIZE_KB 256
+#define MCU_FLASH_PAGE_SIZE 0x1000
 
 #endif

bsp/nrf5x/nrf52832/template.uvoptx

@@ -120,12 +120,12 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>JL2CM3</Key>
-          <Name>-U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
+          <Name>-U682327541 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
           <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))</Name>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>

bsp/nrf5x/nrf52832/template.uvprojx

@@ -16,9 +16,9 @@
         <TargetCommonOption>
           <Device>nRF52832_xxAA</Device>
           <Vendor>Nordic Semiconductor</Vendor>
-          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.24.1</PackID>
+          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.27.1</PackID>
           <PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
-          <Cpu>IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
+          <Cpu>IRAM(0x20000000,0x00010000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
@@ -274,8 +274,8 @@
               </OCR_RVCT3>
               <OCR_RVCT4>
                 <Type>1</Type>
-                <StartAddress>0x1f000</StartAddress>
-                <Size>0x61000</Size>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x80000</Size>
               </OCR_RVCT4>
               <OCR_RVCT5>
                 <Type>1</Type>
@@ -299,8 +299,8 @@
               </OCR_RVCT8>
               <OCR_RVCT9>
                 <Type>0</Type>
-                <StartAddress>0x200025f8</StartAddress>
-                <Size>0xda08</Size>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
               </OCR_RVCT9>
               <OCR_RVCT10>
                 <Type>0</Type>
@@ -315,7 +315,7 @@
             <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
+            <OneElfS>0</OneElfS>
             <Strict>0</Strict>
             <EnumInt>0</EnumInt>
             <PlainCh>0</PlainCh>
@@ -336,7 +336,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>--reduce_paths</MiscControls>
-              <Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
+              <Define></Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -354,7 +354,7 @@
             <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls>--cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74</MiscControls>
-              <Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
+              <Define></Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>

bsp/nrf5x/nrf52840/board/Kconfig

@@ -7,6 +7,12 @@ config SOC_NRF52840
     select RT_USING_USER_MAIN
     default y
 
+config SOC_NORDIC
+    bool 
+    config SOC_NORDIC
+    default y
+
+
 menu "Onboard Peripheral Drivers"
     config BSP_USING_JLINK_TO_USART
         bool "Enable JLINK TO USART (uart0|RX_PIN:8|TX_PIN:6)"
@@ -55,38 +61,142 @@ menu "On-chip Peripheral Drivers"
         bool "Enable GPIO"
         select RT_USING_PIN
         default y
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        select RT_USING_PWM
+        default n
+        if BSP_USING_PWM
+                config NRFX_PWM_ENABLED
+                int 
+                default 1
+                config BSP_USING_PWM0
+                    bool "Enable PWM0 bus"
+                    default y
+                if BSP_USING_PWM0
+                    config NRFX_PWM0_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM0_CH0
+                        int "PWM0 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM0_CH1
+                        int "PWM0 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM0_CH2
+                        int "PWM0 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM0_CH3
+                        int "PWM0 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM1
+                    bool "Enable PWM1 bus"
+                    default n
+                if BSP_USING_PWM1
+                    config NRFX_PWM1_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM1_CH0
+                        int "PWM1 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM1_CH1
+                        int "PWM1 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM1_CH2
+                        int "PWM1 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM1_CH3
+                        int "PWM1 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM2
+                    bool "Enable PWM2 bus"
+                    default n
+                if BSP_USING_PWM2
+                    config NRFX_PWM2_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM2_CH0
+                        int "PWM2 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM2_CH1
+                        int "PWM2 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM2_CH2
+                        int "PWM2 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM2_CH3
+                        int "PWM2 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+                config BSP_USING_PWM3
+                    bool "Enable PWM3 bus"
+                    default n
+                if BSP_USING_PWM3
+                    config NRFX_PWM3_ENABLED
+                    int 
+                    default 1
+                    config BSP_USING_PWM3_CH0
+                        int "PWM3 channel 0 pin number set"
+                        range 0 47
+                        default 13
+                    config BSP_USING_PWM3_CH1
+                        int "PWM3 channel 1 pin number set"
+                        range 0 47
+                        default 14
+                    config BSP_USING_PWM3_CH2
+                        int "PWM3 channel 2 pin number set"
+                        range 0 47
+                        default 15
+                    config BSP_USING_PWM3_CH3
+                        int "PWM3 channel 3 pin number set"
+                        range 0 47
+                        default 16
+                endif
+        endif
     menuconfig BSP_USING_SOFTDEVICE
         bool "Enable NRF SOFTDEVICE"
         select PKG_USING_NRF5X_SDK
+        select NRFX_CLOCK_ENABLED
         default n
 if BSP_USING_SOFTDEVICE
     config NRFX_CLOCK_ENABLED
-	int "NRFX_CLOCK_ENABLED"
+    int 
     default 1
-	config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-	int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY"
+    config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+    int 
     default 7
-	config NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
-	int "NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY"
-    default 7
-	config NRFX_RTC_ENABLED
-	int "NRFX_RTC_ENABLED"
+    config NRFX_RTC_ENABLED
+    int 
+    default 1
+    config NRFX_RTC1_ENABLED
+    int 
     default 1
-	config NRF_CLOCK_ENABLED
-	int "NRF_CLOCK_ENABLED"
+    config NRF_CLOCK_ENABLED
+    int 
     default 1
-	config NRF_SDH_BLE_ENABLED
-	int "NRF_SDH_BLE_ENABLED"
+    config NRF_SDH_BLE_ENABLED
+    int 
     default 1
-	config NRF_SDH_ENABLED
-	int "NRF_SDH_ENABLED"
+    config NRF_SDH_ENABLED
+    int 
     default 1
-	config NRF_SDH_SOC_ENABLED
-	int "NRF_SDH_SOC_ENABLED"
+    config NRF_SDH_SOC_ENABLED
+    int 
     default 1
-	
 endif
-
     menuconfig BSP_USING_UART
         bool "Enable UART"
         default y

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_eadc.h

@@ -433,11 +433,12 @@ extern "C"
                          u32ModuleNum,\
                          u32Condition,\
                          u16CMPData,\
-                         u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                         u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
+                                                            (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
                                                             (u32Condition) |\
                                                             ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
                                                             (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
-                                                            EADC_CMP_ADCMPEN_Msk))
+                                                            EADC_CMP_ADCMPEN_Msk)))
 
 /**
   * @brief Configure the comparator 1 and enable it.
@@ -458,11 +459,12 @@ extern "C"
                          u32ModuleNum,\
                          u32Condition,\
                          u16CMPData,\
-                         u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                         u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
+                                                            (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
                                                             (u32Condition) |\
                                                             ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
                                                             (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
-                                                            EADC_CMP_ADCMPEN_Msk))
+                                                            EADC_CMP_ADCMPEN_Msk)))
 
 /**
   * @brief Configure the comparator 2 and enable it.
@@ -483,11 +485,12 @@ extern "C"
                          u32ModuleNum,\
                          u32Condition,\
                          u16CMPData,\
-                         u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                         u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
+                                                            (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
                                                             (u32Condition) |\
                                                             ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
                                                             (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
-                                                            EADC_CMP_ADCMPEN_Msk))
+                                                            EADC_CMP_ADCMPEN_Msk)))
 
 /**
   * @brief Configure the comparator 3 and enable it.
@@ -508,11 +511,12 @@ extern "C"
                          u32ModuleNum,\
                          u32Condition,\
                          u16CMPData,\
-                         u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                         u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\
+                                                            (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
                                                             (u32Condition) |\
                                                             ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
                                                             (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
-                                                            EADC_CMP_ADCMPEN_Msk))
+                                                            EADC_CMP_ADCMPEN_Msk)))
 
 /**
   * @brief Enable the compare window mode.

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_qspi.h

@@ -95,6 +95,15 @@ extern "C"
   */
 #define QSPI_TRIGGER_TX_PDMA(qspi)   ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
 
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define QSPI_TRIGGER_TX_RX_PDMA(qspi)   ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk))
+
 /**
   * @brief      Disable RX PDMA transfer.
   * @param[in]  qspi The pointer of the specified QSPI module.
@@ -113,6 +122,15 @@ extern "C"
   */
 #define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
 
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
+
 /**
   * @brief      Get the count of available data in RX FIFO.
   * @param[in]  qspi The pointer of the specified QSPI module.

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_spi.h

@@ -133,6 +133,15 @@ extern "C"
   */
 #define SPI_TRIGGER_TX_PDMA(spi)   ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
 
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_TRIGGER_TX_RX_PDMA(spi)   ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk))
+
 /**
   * @brief      Disable RX PDMA transfer.
   * @param[in]  spi The pointer of the specified SPI module.
@@ -151,6 +160,15 @@ extern "C"
   */
 #define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
 
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
+
 /**
   * @brief      Get the count of available data in RX FIFO.
   * @param[in]  spi The pointer of the specified SPI module.

bsp/nuvoton/libraries/m480/StdDriver/inc/nu_usci_spi.h

@@ -361,6 +361,15 @@ extern "C"
   */
 #define USPI_TRIGGER_TX_PDMA(uspi)   ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
 
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_TRIGGER_TX_RX_PDMA(uspi)   ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
+
 /**
   * @brief      Disable RX PDMA transfer.
   * @param[in]  uspi The pointer of the specified USCI_SPI module.
@@ -379,6 +388,15 @@ extern "C"
   */
 #define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
 
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  * \hideinitializer
+  */
+#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk))
+
 uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock);
 void USPI_Close(USPI_T *uspi);
 void USPI_ClearRxBuf(USPI_T *uspi);

bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c

@@ -165,8 +165,8 @@ static void pm_run(struct rt_pm *pm, rt_uint8_t mode)
 
     SYS_UnlockReg();
 
-    /* Switch run mdoe frequency using PLL + HXT if HXT is enabled.
-       Otherwise, the systme clock will use PLL + HIRC. */
+    /* Switch run mode frequency using PLL + HXT if HXT is enabled.
+       Otherwise, the system clock will use PLL + HIRC. */
     switch (mode)
     {
     case PM_RUN_MODE_HIGH_SPEED:
@@ -209,7 +209,7 @@ static void hw_timer_init(void)
     CLK_EnableModuleClock(PM_TIMER_MODULE);
     SYS_LockReg();
 
-    /* Initialise timer and enable wakeup function. */
+    /* Initialize timer and enable wakeup function. */
     TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1);
     TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0);
     TIMER_EnableInt(PM_TIMER);
@@ -262,7 +262,7 @@ static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
     if (timeout == RT_TICK_MAX)
         return;
 
-    /* start pm timer to compenstate the os tick in power down mode */
+    /* start pm timer to compensate the os tick in power down mode */
     tick = pm_tick_from_os_tick(timeout);
     TIMER_SET_CMP_VALUE(PM_TIMER, tick);
     TIMER_Start(PM_TIMER);
@@ -277,7 +277,7 @@ static void pm_timer_stop(struct rt_pm *pm)
 }
 
 
-/* pm device driver initialise. */
+/* pm device driver initialize. */
 int rt_hw_pm_init(void)
 {
     rt_uint8_t timer_mask;

bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c

@@ -166,7 +166,7 @@ static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_
     if ((irqindex = nu_find_irqindex(pin)) >= 0)
         goto exit_nu_gpio_attach_irq;
 
-    // Find avaiable index of pin in pool.
+    // Find available index of pin in pool.
     if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM)  // Count Trailing Ones ==> Find First Zero
         goto exit_nu_gpio_attach_irq;