FPToFP: opt timing

src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala

@@ -12,14 +12,16 @@ class FPToFP extends FPUPipelineModule{
 
   override def latency: Int = FunctionUnit.f2iCfg.latency.latencyVal.get
 
-  val ctrl = io.in.bits.uop.ctrl.fpu
+  val ctrlIn = io.in.bits.uop.ctrl.fpu
+  val ctrl = S1Reg(ctrlIn)
   val inTag = ctrl.typeTagIn
   val outTag = ctrl.typeTagOut
-  val src1 = unbox(io.in.bits.src(0), inTag, None)
-  val src2 = unbox(io.in.bits.src(1), inTag, None)
   val wflags = ctrl.wflags
+  val src1 = S1Reg(unbox(io.in.bits.src(0), ctrlIn.typeTagIn, None))
+  val src2 = S1Reg(unbox(io.in.bits.src(1), ctrlIn.typeTagIn, None))
+  val rmReg = S1Reg(rm)
 
-  val signNum = Mux(rm(1), src1 ^ src2, Mux(rm(0), ~src2, src2))
+  val signNum = Mux(rmReg(1), src1 ^ src2, Mux(rmReg(0), ~src2, src2))
   val fsgnj = Cat(signNum(fLen), src1(fLen-1, 0))
 
   val fsgnjMux = Wire(new Bundle() {
@@ -32,7 +34,7 @@ class FPToFP extends FPUPipelineModule{
   val dcmp = Module(new CompareRecFN(maxExpWidth, maxSigWidth))
   dcmp.io.a := src1
   dcmp.io.b := src2
-  dcmp.io.signaling := !rm(1)
+  dcmp.io.signaling := !rmReg(1)
 
   val lt = dcmp.io.lt || (dcmp.io.a.asSInt() < 0.S && dcmp.io.b.asSInt() >= 0.S)
 
@@ -41,7 +43,7 @@ class FPToFP extends FPUPipelineModule{
     val isnan2 = maxType.isNaN(src2)
     val isInvalid = maxType.isSNaN(src1) || maxType.isSNaN(src2)
     val isNaNOut = isnan1 && isnan2
-    val isLHS = isnan2 || rm(0) =/= lt && !isnan1
+    val isLHS = isnan2 || rmReg(0) =/= lt && !isnan1
     fsgnjMux.exc := isInvalid << 4
     fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, src1, src2))
   }
@@ -67,7 +69,7 @@ class FPToFP extends FPUPipelineModule{
         when(outTag === typeTag(outType).U && (typeTag(outType) == 0).B || (outTag < inTag)){
           val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
           narrower.io.in := src1
-          narrower.io.roundingMode := rm
+          narrower.io.roundingMode := rmReg
           narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
           val narrowed = sanitizeNaN(narrower.io.out, outType)
           mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
@@ -77,11 +79,6 @@ class FPToFP extends FPUPipelineModule{
     }
   }
 
-  var resVec = Seq(mux)
-  for(i <- 1 to latency){
-    resVec = resVec :+ PipelineReg(i)(resVec(i-1))
-  }
-
-  io.out.bits.data := resVec.last.data
-  fflags := resVec.last.exc
+  io.out.bits.data := S2Reg(mux.data)
+  fflags := S2Reg(mux.exc)
 }