vector: add the connection for permutation

src/main/scala/xiangshan/Parameters.scala

@@ -323,6 +323,9 @@ case class XSCoreParameters
         ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
         ExeUnitParams(Seq(VimacCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
       ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
+      IssueBlockParams(Seq(
+        ExeUnitParams(Seq(VppuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
+      ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2),
       IssueBlockParams(Seq(
         ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))),
         ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))),

src/main/scala/xiangshan/backend/Bundles.scala

@@ -262,7 +262,8 @@ object Bundles {
     // vector load/store
     val nf        = Nf()
 
-    val needScalaSrc = Bool()
+    val needScalaSrc       = Bool()
+    val permImmTruncate    = Bool() // opivi
 
     val isReverse = Bool() // vrsub, vrdiv
     val isExt     = Bool()

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -774,7 +774,8 @@ class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstan
   decodedInst.vpu.vlmul := io.enq.vtype.vlmul
   decodedInst.vpu.vm    := inst.VM
   decodedInst.vpu.nf    := inst.NF
-  decodedInst.vpu.needScalaSrc := Category.needScalaSrc(inst.VCATEGORY)
+  decodedInst.vpu.needScalaSrc       := Category.needScalaSrc(inst.VCATEGORY)
+  decodedInst.vpu.permImmTruncate    := Category.permImmTruncate(inst.VCATEGORY)
   decodedInst.vpu.isReverse := needReverseInsts.map(_ === inst.ALL).reduce(_ || _)
   decodedInst.vpu.isExt     := vextInsts.map(_ === inst.ALL).reduce(_ || _)
   decodedInst.vpu.isNarrow  := narrowInsts.map(_ === inst.ALL).reduce(_ || _)

src/main/scala/xiangshan/backend/fu/FuConfig.scala

@@ -6,7 +6,7 @@ import xiangshan.ExceptionNO._
 import xiangshan.SelImm
 import xiangshan.backend.Std
 import xiangshan.backend.fu.fpu.{FDivSqrt, FMA, FPToFP, FPToInt, IntToFP}
-import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VIAluFix, VIMacU, VSetRiWi, VSetRiWvf, VSetRvfWvf}
+import xiangshan.backend.fu.wrapper.{Alu, BranchUnit, DivUnit, JumpUnit, MulUnit, VIAluFix, VIMacU, VPPU, VSetRiWi, VSetRiWvf, VSetRvfWvf}
 import xiangshan.backend.Bundles.ExuInput
 import xiangshan.backend.datapath.DataConfig._
 
@@ -493,6 +493,23 @@ object FuConfig {
     dataBits = 128,
   )
 
+  val VppuCfg = FuConfig (
+    name = "vppu",
+    fuType = FuType.vppu,
+    fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")),
+    srcData = Seq(
+      Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()),  // vs1, vs2, vd_old, v0, vtype&vl
+    ),
+    piped = true,
+    writeVecRf = true,
+    writeVxsat = true,
+    latency = CertainLatency(1),
+    vconfigWakeUp = true,
+    maskWakeUp = true,
+    dataBits = 128,
+    immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS),
+  )
+
   val VipuCfg: FuConfig = FuConfig (
     name = "vipu",
     fuType = FuType.vipu,
@@ -545,7 +562,7 @@ object FuConfig {
   )
 
   def VecArithFuConfigs = Seq(
-    VialuCfg, VimacCfg, VipuCfg, VfpuCfg
+    VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfpuCfg
   )
 }
 

src/main/scala/xiangshan/backend/fu/vector/Bundles.scala

@@ -133,5 +133,8 @@ object Bundles {
     def needScalaSrc(category: UInt) : Bool = {
       Seq(OPIVI, OPIVX, OPFVF, OPMVX).map(_ === category).reduce(_ || _)
     }
+    def permImmTruncate(category: UInt) : Bool = {
+      Seq(OPIVI).map(_ === category).reduce(_ || _)
+    }
   }
 }

src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala

+package xiangshan.backend.fu.wrapper
+
+import chipsalliance.rocketchip.config.Parameters
+import chisel3._
+import chisel3.util._
+import utils.XSError
+import xiangshan.backend.fu.FuConfig
+import xiangshan.backend.fu.vector.Bundles.VSew
+import xiangshan.backend.fu.vector.utils.VecDataSplitModule
+import xiangshan.backend.fu.vector.{Mgu, Utils, VecPipedFuncUnit, VecSrcTypeModule}
+import xiangshan.SrcType
+import yunsuan.encoding.Opcode.VimacOpcode
+import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType}
+import yunsuan.{OpType, VpermType}
+import yunsuan.vector.perm.Permutation
+
+class VPermSrcTypeModule extends VecSrcTypeModule {
+  private val srcVdType = Wire(new Bundle{
+    val srcType2 = UInt(4.W)
+    val srcType1 = UInt(4.W)
+    val vdType = UInt(4.W)
+  })
+  srcVdType := VpermType.getSrcVdType(fuOpType, vsew)
+
+  io.out.vs2Type := srcVdType.srcType2
+  io.out.vs1Type := srcVdType.srcType1
+  io.out.vdType  := srcVdType.vdType
+}
+
+class VPPU(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) {
+  XSError(io.in.valid && io.in.bits.ctrl.fuOpType === VpermType.dummy, "VpermType OpType not supported")
+
+  // params alias
+  private val dataWidth = cfg.dataBits
+  private val dataWidthOfDataModule = 64
+  private val numVecModule = dataWidth / dataWidthOfDataModule
+  private val vppuNeedClearMask = (VpermType.vcompress === io.in.bits.ctrl.fuOpType) && (vuopIdx(log2Up(MaxUopSize)-1,1) === 0.U)
+  private val mask = Mux(vppuNeedClearMask, 0.U, outSrcMask)
+
+  // io alias
+  private val opcode  = VpermType.getOpcode(fuOpType)
+  
+  // modules
+  private val typeMod = Module(new VIMacSrcTypeModule)
+  private val vperms = Module(new Permutation)
+
+  /**
+    * [[typeMod]]'s in connection
+    */
+  typeMod.io.in.fuOpType := fuOpType
+  typeMod.io.in.vsew := vsew
+  typeMod.io.in.isReverse := isReverse
+  typeMod.io.in.isExt := isExt
+  typeMod.io.in.isDstMask := vecCtrl.isDstMask
+  typeMod.io.in.isMove := isMove
+
+  /**
+    * [[vperms]]'s in connection
+    */
+  vperms.io match {
+    case subIO =>
+      subIO.in.valid            := io.in.valid
+      subIO.in.bits.opcode.op   := opcode
+      subIO.in.bits.info.vm     := vm
+      subIO.in.bits.info.ma     := vma
+      subIO.in.bits.info.ta     := vta
+      subIO.in.bits.info.vlmul  := vlmul
+      subIO.in.bits.info.vl     := srcVConfig.vl
+      subIO.in.bits.info.vstart := vstart
+      subIO.in.bits.info.uopIdx := vuopIdx
+      subIO.in.bits.info.vxrm   := vxrm
+      subIO.in.bits.srcType(0)  := typeMod.io.out.vs2Type
+      subIO.in.bits.srcType(1)  := typeMod.io.out.vs1Type
+      subIO.in.bits.vdType      := typeMod.io.out.vdType
+      subIO.in.bits.vs1         := Mux(vecCtrl.permImmTruncate, vs1(4,0), vs1)
+      subIO.in.bits.vs2         := vs2
+      subIO.in.bits.old_vd      := oldVd
+      subIO.in.bits.mask        := mask
+  }
+
+  io.out.bits.res.data := vperms.io.out.vd
+  io.out.bits.res.vxsat.foreach(_ := vperms.io.out.vxsat)
+}