riscv_core_with_axi_master.v

`timescale 1 ns / 1 ps

module riscv_core_with_axi_master (
		input wire  m00_axi_aclk,
		input wire  m00_axi_aresetn,
		output wire [31 : 0] m00_axi_awaddr,
		output wire [2 : 0] m00_axi_awprot,
		output wire  m00_axi_awvalid,
		input wire  m00_axi_awready,
		output wire [31 : 0] m00_axi_wdata,
		output wire [3 : 0] m00_axi_wstrb,
		output wire  m00_axi_wvalid,
		input wire  m00_axi_wready,
		input wire [1 : 0] m00_axi_bresp,
		input wire  m00_axi_bvalid,
		output wire  m00_axi_bready,
		output wire [31 : 0] m00_axi_araddr,
		output wire [2 : 0] m00_axi_arprot,
		output wire  m00_axi_arvalid,
		input wire  m00_axi_arready,
		input wire [31 : 0] m00_axi_rdata,
		input wire [1 : 0] m00_axi_rresp,
		input wire  m00_axi_rvalid,
		output wire  m00_axi_rready
);

	reg			axi_awvalid;	assign m00_axi_awvalid = axi_awvalid;
	reg [31:0] 	axi_awaddr;		assign m00_axi_awaddr = axi_awaddr;
								assign m00_axi_awprot = 3'b000;

	reg			axi_wvalid;		assign m00_axi_wvalid = axi_wvalid;
	reg [31:0] 	axi_wdata;		assign m00_axi_wdata = axi_wdata;
	reg [3:0]   axi_wstrb;		assign m00_axi_wstrb = axi_wstrb;

								assign m00_axi_bready = 1'b1;

	reg			axi_arvalid;	assign m00_axi_arvalid = axi_arvalid;
	reg [31:0] 	axi_araddr;		assign m00_axi_araddr = axi_araddr;
								assign m00_axi_arprot = 3'b001;

								assign m00_axi_rready = 1'b1;

    wire wWrite, wRead, wReadReady, wWriteReady;
    wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
	wire [3:0]  bWriteMask;

	wire [4:0]  regno;
    wire [3:0]  regena;
    wire [31:0] regwrdata;
    wire        regwren;
    wire [31:0] regrddata;
    wire [4:0]  regno2;
    wire [3:0]  regena2;
    wire [31:0] regwrdata2;
    wire        regwren2;
    wire [31:0] regrddata2;

	reg [31:0] lastreadaddr;
	reg		   lastread;

	always @(posedge m00_axi_aclk)
	if (~m00_axi_aresetn) begin
		lastreadaddr <= 0;
		lastread <= 0;
	end else begin
		lastreadaddr <= bReadAddr;
		lastread <= wRead;
	end

	wire isramaddr = (lastreadaddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */
	assign bReadData = isramaddr ? bReadDataRam : m00_axi_rdata;
	assign wReadReady = isramaddr ? lastread : m00_axi_rvalid;

	wire isramwriteaddr = (bWriteAddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */
	wire isramreadaddr  = (bReadAddr & 32'hfff0_0000) == 32'h0000_0000; /* 1MB ram addr */

    wire [29:0] ramaddr;
    assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2];

	reg [4:0] lastregno;
	reg [4:0] lastregno2;

	always @(posedge m00_axi_aclk) begin
		lastregno <= regno;
		lastregno2 <= regno2;
	end

    regfile    regs(regno, regena, m00_axi_aclk, regwrdata, regwren, regrddata);
    regfile    regs2(regno2, regena2, m00_axi_aclk, regwrdata2, regwren2, regrddata2);

`define ALTERA

`ifdef ALTERA
	ram4kB    ram(.clock(m00_axi_aclk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(isramwriteaddr ? wWrite : 1'b0), .q(bReadDataRam));
`else
    ram4KB  ram(.clka(m00_axi_aclk), .ena(1'b1), .addra(ramaddr), .wea((isramwriteaddr && wWrite)?(~bWriteMask):4'b0), .dina(bWriteData) , .douta(bReadDataRam));
`endif
	riscv_core_v5 core(
				m00_axi_aclk, 
				m00_axi_aresetn, 
				wWrite, 
				bWriteAddr, 
				bWriteData, 
				bWriteMask, 
				wWriteReady,
				wRead, 
				bReadAddr, 
				bReadData, 
				wReadReady,
                regno, 
				regena, 
				regwrdata, 
				regwren, 
				(lastregno == 0) ? 0 : regrddata,
				regno2, 
				regena2, 
				regwrdata2, 
				regwren2, 
				(lastregno2 == 0) ? 0 : regrddata2
				);


	//Write Address
	wire writeaxi = (wWrite && ~isramwriteaddr);
	reg [31:0] awaddr;
	reg awvalid;
	always @(posedge m00_axi_aclk)
	if (~m00_axi_aresetn) begin
		awvalid <= 1'b0;
	end else if (writeaxi) begin
		awaddr <= bWriteAddr;
		awvalid <= 1'b1;
	end else if (m00_axi_awready) begin
		awvalid <= 1'b0;
	end

	always @(wWrite or awvalid or bWriteAddr or awaddr)
	begin
		axi_awvalid = writeaxi ? 1'b1 : awvalid;
		axi_awaddr = wWrite ? bWriteAddr : awaddr;
	end

	/* Write Data */
	reg [31:0] waddr;
	reg [31:0] wdata;
	reg [3:0]  wstrb;
	reg		   wvalid;
	reg		   write_local;
	always @(posedge m00_axi_aclk)
	begin
		if (~m00_axi_aresetn) begin
			wvalid <= 1'b0;
		end else if (writeaxi) begin
			waddr <= bWriteAddr;
			wdata <= bWriteData;
			wstrb <= ~bWriteMask;
			wvalid <= 1'b1;
		end if (m00_axi_wready) begin
			wvalid <= 1'b0;
		end
		if (~m00_axi_aresetn) begin
			write_local <= 1'b0;
		end else if (wWrite) begin
			if (isramwriteaddr) begin
				write_local <= 1;
			end else begin
				write_local <= 0;
			end
		end
	end

	reg writeready;
	assign wWriteReady = writeready;
	always @(posedge m00_axi_aclk)
	if (~m00_axi_aresetn)
		writeready <= 1'b0;
	else
		writeready <= m00_axi_wready || write_local || isramwriteaddr;

	always @(wWrite or wvalid or bWriteData or wdata or bWriteMask or wstrb)
	begin
		axi_wvalid = writeaxi ? 1'b1 : wvalid;
		axi_wdata = writeaxi  ? bWriteData : wdata;
		axi_wstrb = writeaxi  ? ~bWriteMask : wstrb;
	end

	wire readaxi = wRead && ~isramreadaddr;
	//Read Address
	reg [31:0] araddr;
	reg arvalid;
	always @(posedge m00_axi_aclk)
	if (~m00_axi_aresetn) begin
		arvalid <= 1'b0;
	end else if (readaxi) begin
		araddr <= bReadAddr;
		arvalid <= 1'b1;
	end else if (m00_axi_arready) begin
		arvalid <= 1'b0;
	end

	always @(wRead or arvalid or bReadAddr or araddr)
	begin
		axi_arvalid = readaxi ? 1'b1 : arvalid;
		axi_araddr = wRead ? bReadAddr : araddr;
	end

endmodule