terris_main_asm.v

(* 
  HDL4SE = "LCOM",
  CLSID = "9B0B3D25-346D-48B9-ABB9-ED755910425D",
  softmodule = "hdl4se"
*)
module hdl4se_mux2
#(
  parameter WIDTH = 8
)
(
  input  sel,
  input  [(WIDTH-1):0]  in0,
  input  [(WIDTH-1):0]  in1,
  output  [(WIDTH-1):0]  data
)
;
  wire sel;
  wire [(WIDTH-1):0]  in0;
  wire [(WIDTH-1):0]  in1;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "041F3AA1-97CD-4412-9E8E-D04ADF291AE2",
  softmodule = "hdl4se"
*)
module hdl4se_mux4
#(
  parameter WIDTH = 8
)
(
  input  [1:0]  sel,
  input  [(WIDTH-1):0]  in0,
  input  [(WIDTH-1):0]  in1,
  input  [(WIDTH-1):0]  in2,
  input  [(WIDTH-1):0]  in3,
  output  [(WIDTH-1):0]  data
)
;
  wire [1:0]  sel;
  wire [(WIDTH-1):0]  in0;
  wire [(WIDTH-1):0]  in1;
  wire [(WIDTH-1):0]  in2;
  wire [(WIDTH-1):0]  in3;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA",
  softmodule = "hdl4se"
*)
module hdl4se_mux8
#(
  parameter WIDTH = 8
)
(
  input  [2:0]  sel,
  input  [(WIDTH-1):0]  in0,
  input  [(WIDTH-1):0]  in1,
  input  [(WIDTH-1):0]  in2,
  input  [(WIDTH-1):0]  in3,
  input  [(WIDTH-1):0]  in4,
  input  [(WIDTH-1):0]  in5,
  input  [(WIDTH-1):0]  in6,
  input  [(WIDTH-1):0]  in7,
  output  [(WIDTH-1):0]  data
)
;
  wire [2:0]  sel;
  wire [(WIDTH-1):0]  in0;
  wire [(WIDTH-1):0]  in1;
  wire [(WIDTH-1):0]  in2;
  wire [(WIDTH-1):0]  in3;
  wire [(WIDTH-1):0]  in4;
  wire [(WIDTH-1):0]  in5;
  wire [(WIDTH-1):0]  in6;
  wire [(WIDTH-1):0]  in7;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "69B4A095-0644-4B9E-9CF0-295474D7C243",
  softmodule = "hdl4se"
*)
module hdl4se_mux16
#(
  parameter WIDTH = 8
)
(
  input  [3:0]  sel,
  input  [(WIDTH-1):0]  in0,
  input  [(WIDTH-1):0]  in1,
  input  [(WIDTH-1):0]  in2,
  input  [(WIDTH-1):0]  in3,
  input  [(WIDTH-1):0]  in4,
  input  [(WIDTH-1):0]  in5,
  input  [(WIDTH-1):0]  in6,
  input  [(WIDTH-1):0]  in7,
  input  [(WIDTH-1):0]  in8,
  input  [(WIDTH-1):0]  in9,
  input  [(WIDTH-1):0]  in10,
  input  [(WIDTH-1):0]  in11,
  input  [(WIDTH-1):0]  in12,
  input  [(WIDTH-1):0]  in13,
  input  [(WIDTH-1):0]  in14,
  input  [(WIDTH-1):0]  in15,
  output  [(WIDTH-1):0]  data
)
;
  wire [3:0]  sel;
  wire [(WIDTH-1):0]  in0;
  wire [(WIDTH-1):0]  in1;
  wire [(WIDTH-1):0]  in2;
  wire [(WIDTH-1):0]  in3;
  wire [(WIDTH-1):0]  in4;
  wire [(WIDTH-1):0]  in5;
  wire [(WIDTH-1):0]  in6;
  wire [(WIDTH-1):0]  in7;
  wire [(WIDTH-1):0]  in8;
  wire [(WIDTH-1):0]  in9;
  wire [(WIDTH-1):0]  in10;
  wire [(WIDTH-1):0]  in11;
  wire [(WIDTH-1):0]  in12;
  wire [(WIDTH-1):0]  in13;
  wire [(WIDTH-1):0]  in14;
  wire [(WIDTH-1):0]  in15;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "29D9C8D6-810E-41D0-BCEF-A5B86EE1EE01",
  softmodule = "hdl4se"
*)
module hdl4se_split2
#(
  parameter INPUTWIDTH = 16,
  parameter OUTPUTWIDTH0 = 8,
  parameter OUTPUTFROM0 = 0,
  parameter OUTPUTWIDTH1 = 8,
  parameter OUTPUTFROM1 = 8
)
(
  input  [(INPUTWIDTH-1):0]  wirein,
  output  [(OUTPUTWIDTH0-1):0]  wireout0,
  output  [(OUTPUTWIDTH1-1):0]  wireout1
)
;
  wire [(INPUTWIDTH-1):0]  wirein;
  wire [(OUTPUTWIDTH0-1):0]  wireout0;
  wire [(OUTPUTWIDTH1-1):0]  wireout1;
  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
  assign wireout1 = wirein [(OUTPUTWIDTH1+(OUTPUTFROM1-1)):OUTPUTFROM1] ;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "1d56a7ee-483d-415e-ba3c-9bd83d3d550e",
  softmodule = "hdl4se"
*)
module hdl4se_split1
#(
  parameter INPUTWIDTH = 16,
  parameter OUTPUTWIDTH0 = 8,
  parameter OUTPUTFROM0 = 0
)
(
  input  [(INPUTWIDTH-1):0]  wirein,
  output  [(OUTPUTWIDTH0-1):0]  wireout0
)
;
  wire [(INPUTWIDTH-1):0]  wirein;
  wire [(OUTPUTWIDTH0-1):0]  wireout0;
  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "D5152459-6798-49C8-8376-21EBE8A9EE3C",
  softmodule = "hdl4se"
*)
module hdl4se_split4
#(
  parameter INPUTWIDTH = 32,
  parameter OUTPUTWIDTH0 = 8,
  parameter OUTPUTFROM0 = 0,
  parameter OUTPUTWIDTH1 = 8,
  parameter OUTPUTFROM1 = 8,
  parameter OUTPUTWIDTH2 = 8,
  parameter OUTPUTFROM2 = 16,
  parameter OUTPUTWIDTH3 = 8,
  parameter OUTPUTFROM3 = 24
)
(
  input  [(INPUTWIDTH-1):0]  wirein,
  output  [(OUTPUTWIDTH0-1):0]  wireout0,
  output  [(OUTPUTWIDTH1-1):0]  wireout1,
  output  [(OUTPUTWIDTH2-1):0]  wireout2,
  output  [(OUTPUTWIDTH3-1):0]  wireout3
)
;
  wire [(INPUTWIDTH-1):0]  wirein;
  wire [(OUTPUTWIDTH0-1):0]  wireout0;
  wire [(OUTPUTWIDTH1-1):0]  wireout1;
  wire [(OUTPUTWIDTH2-1):0]  wireout2;
  wire [(OUTPUTWIDTH3-1):0]  wireout3;
  assign wireout0 = wirein [(OUTPUTWIDTH0+(OUTPUTFROM0-1)):OUTPUTFROM0] ;
  assign wireout1 = wirein [(OUTPUTWIDTH1+(OUTPUTFROM1-1)):OUTPUTFROM1] ;
  assign wireout2 = wirein [(OUTPUTWIDTH2+(OUTPUTFROM2-1)):OUTPUTFROM2] ;
  assign wireout3 = wirein [(OUTPUTWIDTH3+(OUTPUTFROM3-1)):OUTPUTFROM3] ;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0",
  softmodule = "hdl4se"
*)
module hdl4se_bind2
#(
  parameter INPUTWIDTH0 = 8,
  parameter INPUTWIDTH1 = 8
)
(
  input  [(INPUTWIDTH0-1):0]  wirein0,
  input  [(INPUTWIDTH1-1):0]  wirein1,
  output  [(INPUTWIDTH0+(INPUTWIDTH1-1)):0]  wireout
)
;
  wire [(INPUTWIDTH0-1):0]  wirein0;
  wire [(INPUTWIDTH1-1):0]  wirein1;
  wire [(INPUTWIDTH0+(INPUTWIDTH1-1)):0]  wireout;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "D1F303E2-3ED1-42FD-8762-3AA623DA901E",
  softmodule = "hdl4se"
*)
module hdl4se_bind3
#(
  parameter INPUTWIDTH0 = 8,
  parameter INPUTWIDTH1 = 8,
  parameter INPUTWIDTH2 = 8
)
(
  input  [(INPUTWIDTH0-1):0]  wirein0,
  input  [(INPUTWIDTH1-1):0]  wirein1,
  input  [(INPUTWIDTH2-1):0]  wirein2,
  output  [(INPUTWIDTH0+(INPUTWIDTH1+(INPUTWIDTH2-1))):0]  wireout
)
;
  wire [(INPUTWIDTH0-1):0]  wirein0;
  wire [(INPUTWIDTH1-1):0]  wirein1;
  wire [(INPUTWIDTH2-1):0]  wirein2;
  wire [(INPUTWIDTH0+(INPUTWIDTH1+(INPUTWIDTH2-1))):0]  wireout;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "0234ECE7-A9C5-406B-9AE7-4841EA0DF7C9",
  softmodule = "hdl4se"
*)
module hdl4se_bind4
#(
  parameter WIDTH0 = 8,
  parameter WIDTH1 = 8,
  parameter WIDTH2 = 8,
  parameter WIDTH3 = 8
)
(
  input  [(WIDTH0-1):0]  wirein0,
  input  [(WIDTH1-1):0]  wirein1,
  input  [(WIDTH2-1):0]  wirein2,
  input  [(WIDTH3-1):0]  wirein3,
  output  [(WIDTH0+(WIDTH1+(WIDTH2+(WIDTH3-1)))):0]  wireout
)
;
  wire [(WIDTH0-1):0]  wirein0;
  wire [(WIDTH1-1):0]  wirein1;
  wire [(WIDTH2-1):0]  wirein2;
  wire [(WIDTH3-1):0]  wirein3;
  wire [(WIDTH0+(WIDTH1+(WIDTH2+(WIDTH3-1)))):0]  wireout;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "dffb1080-8b92-4b42-a607-d1b377c27bb1",
  softmodule = "hdl4se"
*)
module hdl4se_ram1p
#(
  parameter WIDTH = 8,
  parameter ADDRWIDTH = 8
)
(
  input  wClk,
  input  wWrite,
  input  [(ADDRWIDTH-1):0]  bWriteAddr,
  input  [(WIDTH-1):0]  bWriteData,
  input  [(ADDRWIDTH-1):0]  bReadAddr,
  output  [(WIDTH-1):0]  bReadData
)
;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "d26dddb3-0fdf-48c6-b4f3-4042eff8ca79",
  softmodule = "hdl4se"
*)
module hdl4se_ram2p
#(
  parameter WIDTH = 8,
  parameter ADDRWIDTH = 8
)
(
  input  wClk,
  input  wWrite1,
  input  [(ADDRWIDTH-1):0]  bWriteAddr1,
  input  [(WIDTH-1):0]  bWriteData1,
  input  [(ADDRWIDTH-1):0]  bReadAddr1,
  output  [(WIDTH-1):0]  bReadData1,
  input  wWrite2,
  input  [(ADDRWIDTH-1):0]  bWriteAddr2,
  input  [(WIDTH-1):0]  bWriteData2,
  input  [(ADDRWIDTH-1):0]  bReadAddr2,
  output  [(WIDTH-1):0]  bReadData2
)
;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "8FBE5B87-B484-4f95-8291-DBEF86A1C354",
  softmodule = "hdl4se"
*)
module hdl4se_const
#(
  parameter WIDTH = 8,
  parameter VALUE = 8'b0
)
(
  output  [(WIDTH-1):0]  data
)
;
  wire [(WIDTH-1):0]  data;
  assign data = VALUE;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "060FB913-1C0F-4704-8EC2-A08BF5387062",
  softmodule = "hdl4se"
*)
module hdl4se_binop
#(
  parameter INPUTWIDTH0 = 8,
  parameter INPUTWIDTH1 = 8,
  parameter OUTPUTWIDTH = 8,
  parameter OP = 0
)
(
  input  [(INPUTWIDTH0-1):0]  wirein0,
  input  [(INPUTWIDTH1-1):0]  wirein1,
  output  [(OUTPUTWIDTH-1):0]  wireout
)
;
  wire [(INPUTWIDTH0-1):0]  wirein0;
  wire [(INPUTWIDTH1-1):0]  wirein1;
  wire [(OUTPUTWIDTH-1):0]  wireout;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "E6772805-57BB-4b39-A10D-FDA6A4810E3B",
  softmodule = "hdl4se"
*)
module hdl4se_unop
#(
  parameter INPUTWIDTH = 8,
  parameter OUTPUTWIDTH = 8,
  parameter OP = 0
)
(
  input  [(INPUTWIDTH-1):0]  wirein,
  output  [(OUTPUTWIDTH-1):0]  wireout
)
;
  wire [(INPUTWIDTH-1):0]  wirein;
  wire [(OUTPUTWIDTH-1):0]  wireout;
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
  softmodule = "hdl4se"
*)
module hdl4se_reg
#(
  parameter WIDTH = 8
)
(
  input  wClk,
  input  [(WIDTH-1):0]  wirein,
  output  [(WIDTH-1):0]  wireout
)
;
  wire [(WIDTH-1):0]  wirein;
endmodule


module turnleft
(
  input  [63:0]  inblock,
  output  [63:0]  outblock
)
;
  wire [3:0]  b00;
  wire [3:0]  b01;
  wire [3:0]  b02;
  wire [3:0]  b03;
  wire [3:0]  b10;
  wire [3:0]  b11;
  wire [3:0]  b12;
  wire [3:0]  b13;
  wire [3:0]  b20;
  wire [3:0]  b21;
  wire [3:0]  b22;
  wire [3:0]  b23;
  wire [3:0]  b30;
  wire [3:0]  b31;
  wire [3:0]  b32;
  wire [3:0]  b33;
  wire [15:0]  line0;
  wire [15:0]  line1;
  wire [15:0]  line2;
  wire [15:0]  line3;
  assign b00 = inblock [3:0] ;
  assign b01 = inblock [7:4] ;
  assign b02 = inblock [11:8] ;
  assign b03 = inblock [15:12] ;
  assign b10 = inblock [19:16] ;
  assign b11 = inblock [23:20] ;
  assign b12 = inblock [27:24] ;
  assign b13 = inblock [31:28] ;
  assign b20 = inblock [35:32] ;
  assign b21 = inblock [39:36] ;
  assign b22 = inblock [43:40] ;
  assign b23 = inblock [47:44] ;
  assign b30 = inblock [51:48] ;
  assign b31 = inblock [55:52] ;
  assign b32 = inblock [59:56] ;
  assign b33 = inblock [63:60] ;
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline0( b03, b13, b23, b33, line0 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline1( b02, b12, b22, b32, line1 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline2( b01, b11, b21, b31, line2 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline3( b00, b10, b20, b30, line3 );
  hdl4se_bind4 #( 16, 16, 16, 16 ) bindline( line0, line1, line2, line3, outblock );
endmodule


module turnright
(
  input  [63:0]  inblock,
  output  [63:0]  outblock
)
;
  wire [3:0]  b00;
  wire [3:0]  b01;
  wire [3:0]  b02;
  wire [3:0]  b03;
  wire [3:0]  b10;
  wire [3:0]  b11;
  wire [3:0]  b12;
  wire [3:0]  b13;
  wire [3:0]  b20;
  wire [3:0]  b21;
  wire [3:0]  b22;
  wire [3:0]  b23;
  wire [3:0]  b30;
  wire [3:0]  b31;
  wire [3:0]  b32;
  wire [3:0]  b33;
  wire [15:0]  line0;
  wire [15:0]  line1;
  wire [15:0]  line2;
  wire [15:0]  line3;
  assign b00 = inblock [3:0] ;
  assign b01 = inblock [7:4] ;
  assign b02 = inblock [11:8] ;
  assign b03 = inblock [15:12] ;
  assign b10 = inblock [19:16] ;
  assign b11 = inblock [23:20] ;
  assign b12 = inblock [27:24] ;
  assign b13 = inblock [31:28] ;
  assign b20 = inblock [35:32] ;
  assign b21 = inblock [39:36] ;
  assign b22 = inblock [43:40] ;
  assign b23 = inblock [47:44] ;
  assign b30 = inblock [51:48] ;
  assign b31 = inblock [55:52] ;
  assign b32 = inblock [59:56] ;
  assign b33 = inblock [63:60] ;
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline0( b30, b20, b10, b00, line0 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline1( b31, b21, b11, b01, line1 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline2( b32, b22, b12, b02, line2 );
  hdl4se_bind4 #( 4, 4, 4, 4 ) bindline3( b33, b23, b13, b03, line3 );
  hdl4se_bind4 #( 16, 16, 16, 16 ) bindline( line0, line1, line2, line3, outblock );
endmodule


(* 
  CLSID = "158fa52-ca8b-4551-9b87-fc7cff466e2a",
  softmodule = "hdl4se"
*)
module teris_ctrl
(
  input  wClk,
  input  nwReset,
  input  [31:0]  bKeyData,
  input  wStateComplete,
  output  [3:0]  bState,
  output  [31:0]  bScore,
  output  [31:0]  bSpeed,
  output  [31:0]  bLevel,
  output  [63:0]  bNextBlock,
  output  [63:0]  bCurBlock,
  output  [15:0]  bCurBlockPos,
  input  [31:0]  bResult,
  input  [63:0]  bNewNextBlock
)
;
  wire [7:0]  outputx;
  wire [7:0]  outputy;
  wire [3:0]  wirein_state;
  wire [3:0]  wireout_state;
  wire [3:0]  stateAfterFlushToDisp;
  wire [3:0]  stateAfterCheckBlockCanSetTo;
  wire [3:0]  stateAfterCheckLine;
  wire [3:0]  stateAfterCheckKey;
  wire [3:0]  nextstate;
  wire [7:0]  wirein_testx;
  wire [7:0]  wireout_testx;
  wire [7:0]  testxwencheckkey;
  wire [7:0]  wirein_testy;
  wire [7:0]  wireout_testy;
  wire [7:0]  testywencheckkey;
  wire [7:0]  wirein_testid;
  wire [7:0]  wireout_testid;
  wire [7:0]  testidwhencheckkey;
  wire [7:0]  wirein_startline;
  wire [7:0]  wireout_startline;
  wire [31:0]  wirein_checklinecount;
  wire [31:0]  wireout_checklinecount;
  wire [31:0]  checklinecountAfterCheckline;
  wire [7:0]  wirein_testparam;
  wire [7:0]  wireout_testparam;
  wire [31:0]  scoreAfterCheckLine;
  wire [31:0]  scoreAfterCheckKey;
  wire [31:0]  wirein_score;
  wire [31:0]  wireout_score;
  wire [31:0]  linescore;
  wire [31:0]  levelAfterCheckLine;
  wire [31:0]  wirein_level;
  wire [31:0]  wireout_level;
  wire [31:0]  nextlevel;
  wire [31:0]  wirein_speed;
  wire [31:0]  wireout_speed;
  wire [31:0]  scorediv4;
  wire [31:0]  wirein_tick;
  wire [31:0]  wireout_tick;
  wire [7:0]  curposxAfterCheckKey;
  wire [7:0]  curposxAfterCheckLine;
  wire [7:0]  wirein_curposx;
  wire [7:0]  wireout_curposx;
  wire [7:0]  nextblockx;
  wire [7:0]  curposyAfterCheckKey;
  wire [7:0]  curposyAfterCheckLine;
  wire [7:0]  cursoryAfterCheckBlock;
  wire [7:0]  wirein_curposy;
  wire [7:0]  wireout_curposy;
  wire [7:0]  nextblocky;
  wire [63:0]  curblockWhenFlushToDisp;
  wire [63:0]  curblockAfterCheckBlock;
  wire [63:0]  curblockAfterCheckLine;
  wire [63:0]  wirein_curblock;
  wire [63:0]  wireout_curblock;
  wire [63:0]  curblockturnleft;
  wire [63:0]  curblockturnright;
  wire [63:0]  wirein_nextblock;
  wire [63:0]  wireout_nextblock;
  wire [31:0]  wirein_key;
  wire [31:0]  wireout_key;
  wire [31:0]  cur_key;
  assign bState = wireout_state;
  assign bScore = wireout_score;
  assign bSpeed = (32'h1f4-wireout_speed);
  assign bLevel = wireout_level;
  assign bNextBlock = wireout_nextblock;
  assign bCurBlock = ((cur_key [3] )?(curblockturnleft):(wireout_curblock));
  assign wirein_state = ((nwReset)?(nextstate):(0));
  assign stateAfterFlushToDisp = (((wireout_curblock==64'h0))?(7):(((wStateComplete)?(2):(1))));
  assign stateAfterCheckBlockCanSetTo = ((wStateComplete)?((((wireout_testid==0))?(((bResult)?(1):(4))):((((wireout_testid==4))?(((bResult)?(7):(0))):(1))))):(3));
  assign stateAfterCheckLine = ((wStateComplete)?((((bResult<24))?(6):(3))):(5));
  assign stateAfterCheckKey = ((((cur_key [0] ||(cur_key [1] ||cur_key [3] ))&&(wireout_score==0)))?(0):(((((cur_key==0)&&(wireout_tick<=wireout_speed)))?(2):(3))));
  assign wirein_startline = (((wStateComplete&&(bState==5)))?(bResult):(wireout_startline));
  assign wirein_testparam = (((bState==2))?(cur_key):(wireout_testparam));
  assign scoreAfterCheckKey = (((cur_key [3] ||(cur_key [1] ||cur_key [0] )))?((wireout_score-1)):(((cur_key [2] )?((wireout_score+2)):(wireout_score))));
  assign scoreAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_score+(((wireout_checklinecount>0))?(linescore):(0)))):(wireout_score));
  assign wirein_level = ((wStateComplete)?(nextlevel):(wireout_level));
  assign levelAfterCheckLine = (((wStateComplete&&(bResult>=24)))?((wireout_level+wireout_checklinecount)):(wireout_level));
  assign wirein_speed = (((32'h1f4>scorediv4))?((32'd500-scorediv4)):(1));
  assign wirein_tick = ((((nwReset==0)||((cur_key!=0)||(wireout_state!=2))))?(0):((wireout_tick+1)));
  assign wirein_curposx = ((wStateComplete)?(nextblockx):(wireout_curposx));
  assign curposxAfterCheckLine = 8;
  assign wirein_curposy = ((wStateComplete)?(nextblocky):(wireout_curposy));
  assign curposyAfterCheckKey = wireout_curposy;
  assign curposyAfterCheckLine = 0;
  assign cursoryAfterCheckBlock = (((bResult&&(wireout_testid==0)))?((wireout_curposy+1)):(wireout_curposy));
  assign curblockWhenFlushToDisp = (((wireout_curblock==64'b0))?(wireout_nextblock):(wireout_curblock));
  assign curblockAfterCheckBlock = (((wStateComplete&&(bResult&&(wireout_testid==3))))?(curblockturnleft):(wireout_curblock));
  assign curblockAfterCheckLine = (((wStateComplete&&(bResult>=24)))?(wireout_nextblock):(wireout_curblock));
  assign wirein_nextblock = (((wStateComplete&&(wireout_state==7)))?(bNewNextBlock):(wireout_nextblock));
  assign wirein_key = bKeyData;
  assign outputx = (((wireout_state==3))?((wireout_testx+1)):((((wireout_state==6))?(wireout_startline):((wireout_curposx+1)))));
  assign outputy = (((wireout_state==3))?((24+(1-wireout_testy))):((((wireout_state==6))?(8'b0):((24+(1-wireout_curposy))))));
  assign testxwencheckkey = ((cur_key [0] )?((wireout_curposx+1)):(((cur_key [1] )?((wireout_curposx-1)):(wireout_curposx))));
  assign testywencheckkey = (((cur_key [2] ||(cur_key==0)))?((wireout_curposy+1)):(wireout_curposy));
  assign testidwhencheckkey = (((cur_key==0))?((((wireout_tick<=wireout_speed))?(wireout_testid):(0))):(((cur_key [2] )?(0):(((cur_key [1] )?(1):(((cur_key [0] )?(2):(3))))))));
  assign checklinecountAfterCheckline = (((wStateComplete&&(bResult<24)))?((wireout_checklinecount+1)):(wireout_checklinecount));
  assign scorediv4 = wireout_score [31:4] ;
  assign cur_key = (((wireout_key==bKeyData))?(0):(bKeyData));
  hdl4se_bind2 #( 8, 8 ) bindpos( outputx, outputy, bCurBlockPos );
  hdl4se_reg #( 4 ) terris_ctrlstate( wClk, wirein_state, wireout_state );
  hdl4se_mux8 #( 4 ) mux_nextstate( wireout_state, ((wStateComplete)?(7):(0)), stateAfterFlushToDisp, stateAfterCheckKey, stateAfterCheckBlockCanSetTo, ((wStateComplete)?(5):(4))
  , stateAfterCheckLine, ((wStateComplete)?(5):(6)), ((wStateComplete)?(1):(7)), nextstate );
  hdl4se_reg #( 8 ) reg_testx( wClk, wirein_testx, wireout_testx );
  hdl4se_mux8 #( 8 ) mux_testx( wireout_state, wireout_testx, wireout_testx, testxwencheckkey, wireout_testx, wireout_testx
  , 8, wireout_testx, wireout_testx, wirein_testx );
  hdl4se_reg #( 8 ) reg_testy( wClk, wirein_testy, wireout_testy );
  hdl4se_mux8 #( 8 ) mux_testy( wireout_state, wireout_testy, wireout_testy, testywencheckkey, wireout_testy, wireout_testy
  , 0, wireout_testy, wireout_testy, wirein_testy );
  hdl4se_reg #( 8 ) reg_testid( wClk, wirein_testid, wireout_testid );
  hdl4se_mux8 #( 8 ) mux_testid( wireout_state, wireout_testid, wireout_testid, testidwhencheckkey, wireout_testid, wireout_testid
  , 4, wireout_testid, wireout_testid, wirein_testid );
  hdl4se_reg #( 8 ) reg_startline( wClk, wirein_startline, wireout_startline );
  hdl4se_reg #( 32 ) reg_checklinecount( wClk, wirein_checklinecount, wireout_checklinecount );
  hdl4se_mux8 #( 32 ) mux_checklinecount( wireout_state, wireout_checklinecount, wireout_checklinecount, wireout_checklinecount, wireout_checklinecount, 0
  , checklinecountAfterCheckline, wireout_checklinecount, wireout_checklinecount, wirein_checklinecount );
  hdl4se_reg #( 8 ) reg_testparam( wClk, wirein_testparam, wireout_testparam );
  hdl4se_reg #( 32 ) terris_score( wClk, wirein_score, wireout_score );
  hdl4se_mux8 #( 32 ) mux_score( wireout_state, 32'hc8, wireout_score, scoreAfterCheckKey, wireout_score, wireout_score
  , scoreAfterCheckLine, wireout_score, wireout_score, wirein_score );
  hdl4se_mux4 #( 32 ) mux_linescore( (wireout_checklinecount-1), 32'ha, 32'h28, 32'ha0, 32'h280, linescore
   );
  hdl4se_reg #( 32 ) terris_level( wClk, wirein_level, wireout_level );
  hdl4se_mux8 #( 32 ) mux_level( wireout_state, 32'h0, wireout_level, wireout_level, wireout_level, wireout_level
  , levelAfterCheckLine, wireout_level, wireout_level, nextlevel );
  hdl4se_reg #( 32 ) terris_speed( wClk, wirein_speed, wireout_speed );
  hdl4se_reg #( 32 ) terris_tick( wClk, wirein_tick, wireout_tick );
  hdl4se_reg #( 8 ) terris_curposx( wClk, wirein_curposx, wireout_curposx );
  hdl4se_mux8 #( 8 ) mux_blockx( wireout_state, 8, (((wireout_curblock==64'b0))?(8'd8):(wireout_curposx)), curposxAfterCheckKey, ((bResult)?(wireout_testx):(wireout_curposx)), wireout_curposx
  , curposxAfterCheckLine, wireout_curposx, wireout_curposx, nextblockx );
  hdl4se_reg #( 8 ) terris_curposy( wClk, wirein_curposy, wireout_curposy );
  hdl4se_mux8 #( 8 ) mux_blocky( wireout_state, 0, (((wireout_curblock==64'b0))?(8'd0):(wireout_curposy)), wireout_curposy, cursoryAfterCheckBlock, wireout_curposy
  , curposyAfterCheckLine, wireout_curposy, wireout_curposy, nextblocky );
  hdl4se_reg #( 64 ) terris_curblock( wClk, wirein_curblock, wireout_curblock );
  hdl4se_mux8 #( 64 ) mux_curblock( wireout_state, wireout_curblock, curblockWhenFlushToDisp, wireout_curblock, curblockAfterCheckBlock, wireout_curblock
  , curblockAfterCheckLine, wireout_curblock, wireout_curblock, wirein_curblock );
  turnleft curturnleft( wireout_curblock, curblockturnleft );
  turnleft curturnright( wireout_curblock, curblockturnright );
  hdl4se_reg #( 64 ) terris_nextblock( wClk, wirein_nextblock, wireout_nextblock );
  hdl4se_reg #( 31 ) terris_key( wClk, wirein_key, wireout_key );
endmodule


(* 
  CLSID = "d588064-fcd3-43cc-b131-1a64c74d9e86",
  softmodule = "hdl4se"
*)
module flushtodisp
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [5:0]  bFlushReadAddr,
  input  [63:0]  bFlushReadData,
  output  wWrite,
  output  [31:0]  bWriteAddr,
  output  [31:0]  bWriteData,
  input  [31:0]  bCtrlSpeed,
  input  [31:0]  bCtrlLevel,
  input  [31:0]  bCtrlScore,
  input  [63:0]  bNextBlock,
  input  [63:0]  bCurBlock,
  input  [15:0]  bCurBlockPos
)
;
  wire [31:0]  bNextBlockLo;
  wire [31:0]  bNextBlockHi;
  wire [7:0]  blockx;
  wire [7:0]  blocky;
  wire [9:0]  wirein_readaddr;
  wire [9:0]  wireout_readaddr;
  wire [9:0]  wireout_readaddr_delay_1;
  wire [31:0]  selecteddata;
  wire _wWrite;
  wire [31:0]  _bWriteAddr;
  wire [31:0]  _bWriteData;
  wire [9:0]  bWriteDataSel;
  wire [7:0]  y;
  wire [63:0]  curblockline_0;
  wire [63:0]  curblockline;
  wire [63:0]  data;
  wire right;
  assign wirein_readaddr = (((bCtrlState==1))?((wireout_readaddr+1)):(6'b0));
  assign wCtrlStateComplete = (wireout_readaddr==8'd60);
  assign bFlushReadAddr = wireout_readaddr [6:1] ;
  assign wWrite = _wWrite;
  assign bWriteAddr = _bWriteAddr;
  assign bWriteData = _bWriteData;
  assign bNextBlockLo = bNextBlock [31:0] ;
  assign bNextBlockHi = bNextBlock [63:32] ;
  assign blockx = bCurBlockPos [7:0] ;
  assign blocky = bCurBlockPos [15:8] ;
  assign _wWrite = ((bCtrlState==1)&&(bWriteDataSel<=7));
  assign _bWriteAddr = (32'hf0000010+(wireout_readaddr_delay_1*4));
  assign _bWriteData = selecteddata;
  assign bWriteDataSel = (((wireout_readaddr_delay_1<8'd52))?(8'd0):((wireout_readaddr_delay_1-8'd51)));
  assign y = wireout_readaddr_delay_1 [7:1] ;
  assign curblockline_0 = ((((blocky>=y)&&(blocky<(4+y))))?(((bCurBlock>>((blocky-y)*16))&64'hffff)):(64'h0));
  assign curblockline = (((blockx<3))?((curblockline_0>>((3-blockx)*4))):((curblockline_0<<((blockx-3)*4))));
  assign data = (bFlushReadData|curblockline);
  assign right = wireout_readaddr_delay_1 [0] ;
  hdl4se_reg #( 10 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
  hdl4se_reg #( 10 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
  hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel [2:0] , ((right)?(data [63:32] ):(data [31:0] )), bNextBlockLo, bNextBlockHi, 32'h0, 32'h0
  , bCtrlScore, bCtrlLevel, bCtrlSpeed, selecteddata );
endmodule


(* 
  CLSID = "b0d75037-0831-49e5-bbd0-f6b5e07cbb51",
  softmodule = "hdl4se"
*)
module blockwrite
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [5:0]  bBWReadAddr,
  input  [63:0]  bBWReadData,
  output  wBWWrite,
  output  [5:0]  bBWWriteAddr,
  output  [63:0]  bBWWriteData,
  input  [63:0]  bCurBlock,
  input  [15:0]  bCurBlockPos
)
;
  wire [6:0]  wirein_readaddr;
  wire [6:0]  wireout_readaddr;
  wire [6:0]  wireout_readaddr_delay_1;
  wire [7:0]  blockx;
  wire [7:0]  blocky;
  wire [63:0]  curblockline;
  wire [63:0]  curblockline_1;
  assign wirein_readaddr = (((bCtrlState==4))?((wireout_readaddr+1)):(0));
  assign curblockline_1 = ((bCurBlock>>((3-wireout_readaddr_delay_1)*16))&64'hffff);
  assign curblockline = (((blockx<3))?((curblockline_1>>((3-blockx)*4))):((curblockline_1<<((blockx-3)*4))));
  assign wCtrlStateComplete = (wireout_readaddr_delay_1>=4);
  assign bBWReadAddr = (wireout_readaddr+(blocky-4));
  assign wBWWrite = ((wireout_readaddr>0)&&((wireout_readaddr_delay_1>=0)&&(wireout_readaddr_delay_1<=3)));
  assign bBWWriteAddr = (wireout_readaddr_delay_1+(blocky-4));
  assign bBWWriteData = (bBWReadData|curblockline);
  assign blockx = bCurBlockPos [7:0] ;
  assign blocky = bCurBlockPos [15:8] ;
  hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
  hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
endmodule


(* 
  CLSID = "90e0e478-1b32-417e-ab32-e5bdec608431",
  softmodule = "hdl4se"
*)
module canblocksetto
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [5:0]  bCBWReadAddr,
  input  [63:0]  bCBWReadData,
  input  [63:0]  bCurBlock,
  input  [15:0]  bSetToPos,
  output  wCanSet
)
;
  wire [7:0]  wirein_readaddr;
  wire [7:0]  wireout_readaddr;
  wire [7:0]  wireout_readaddr_delay_1;
  wire wirein_cansetto;
  wire wireout_cansetto;
  wire [7:0]  blockx;
  wire [7:0]  blocky;
  wire [63:0]  readdata;
  wire [7:0]  _bCBWReadAddr;
  wire wCanSetCurrent;
  wire wCanSetCurrentPre;
  wire [7:0]  y;
  wire wCanSetCurrent_1;
  wire wCanSetCurrent_1_1;
  wire wCanSetCurrent_1_2;
  wire wCanSetCurrent_1_3;
  wire wCanSetCurrent_2;
  wire wCanSetCurrent_3;
  wire [63:0]  curblockline;
  wire [63:0]  curblockline_0;
  wire [63:0]  curblockline_1;
  wire [63:0]  curblockline_2;
  wire [63:0]  curblockline_3;
  wire [63:0]  curblockline_mask;
  wire [63:0]  curblockline_mask_1;
  wire [63:0]  all1;
  wire [7:0]  shift0;
  wire [7:0]  shift1;
  wire [63:0]  mask0;
  wire [63:0]  mask1;
  wire [63:0]  curblockline_mask_0;
  wire [63:0]  curblockline_mask_1;
  wire cblmask1;
  wire blockxgt3;
  wire [63:0]  curblockline_mask_2;
  wire [63:0]  line;
  assign wCanSet = wireout_cansetto;
  assign bCBWReadAddr = _bCBWReadAddr;
  assign wCtrlStateComplete = ((wireout_readaddr_delay_1>4)||(wireout_cansetto==0));
  assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0));
  assign wirein_cansetto = (((bCtrlState==3))?(wCanSetCurrentPre):(1));
  assign wCanSetCurrentPre = ((((wireout_readaddr>0)&&(wCanSetCurrent==0)))?(0):(wireout_cansetto));
  assign wCanSetCurrent = (((wireout_readaddr_delay_1>=4))?(1):(wCanSetCurrent_1_1));
  assign wCanSetCurrent_1_1 = (((y>=(24+4)))?(1):(wCanSetCurrent_1_2));
  assign wCanSetCurrent_1_2 = (((curblockline==0))?(1):(wCanSetCurrent_1));
  assign wCanSetCurrent_1 = ((((curblockline [15:0] !=0)&&(y<8'd4)))?(0):(wCanSetCurrent_2));
  assign curblockline_0 = (((curblockline [3:0] !=0))?(64'hf):(64'h0));
  assign curblockline_1 = (((curblockline [7:4] !=0))?(64'hf0):(64'h0));
  assign curblockline_2 = (((curblockline [11:8] !=0))?(64'hf00):(64'h0));
  assign curblockline_3 = (((curblockline [15:12] !=0))?(64'hf000):(64'h0));
  assign curblockline_mask = (curblockline_0|(curblockline_1|(curblockline_2|curblockline_3)));
  assign wCanSetCurrent_2 = (((blockx<8'd3))?((((curblockline_mask_0!=0))?(0):(wCanSetCurrent_3))):((((cblmask1&blockxgt3))?(0):(wCanSetCurrent_3))));
  assign wCanSetCurrent_3 = ((bCBWReadData&curblockline_mask_2)==0);
  assign blockx = bSetToPos [7:0] ;
  assign blocky = bSetToPos [15:8] ;
  assign readdata = bCBWReadData;
  assign _bCBWReadAddr = (wireout_readaddr+(blocky-4));
  assign y = (wireout_readaddr_delay_1+blocky);
  assign curblockline = (bCurBlock>>((8'd3-wireout_readaddr_delay_1)*16));
  assign all1 = 64'hffffffffffffffff;
  assign shift0 = (64-((3-blockx)*4));
  assign shift1 = (64-((blockx-8'd3)*4));
  assign mask0 = (all1>>shift0);
  assign mask1 = (all1<<shift1);
  assign curblockline_mask_0 = (curblockline_mask&mask0);
  assign curblockline_mask_1 = (curblockline_mask&mask1);
  assign cblmask1 = (curblockline_mask_1!=0);
  assign blockxgt3 = (blockx>8'd3);
  assign curblockline_mask_2 = (((blockx<8'd3))?((curblockline_mask>>((8'd3-blockx)*4))):((curblockline_mask<<((blockx-8'd3)*4))));
  assign line = bCBWReadData;
  hdl4se_reg #( 8 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
  hdl4se_reg #( 8 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
  hdl4se_reg #( 1 ) reg_cansetto( wClk, wirein_cansetto, wireout_cansetto );
endmodule


(* 
  CLSID = "e39fa78d-7faa-4278-a27f-07b68a99afff",
  softmodule = "hdl4se"
*)
module checkline
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [5:0]  bCKLReadAddr,
  input  [63:0]  bCKLReadData,
  output  [31:0]  bFindLine
)
;
  wire [7:0]  wirein_readaddr;
  wire [7:0]  wireout_readaddr;
  wire [7:0]  wireout_readaddr_delay_1;
  wire block_0;
  wire block_1;
  wire block_2;
  wire block_3;
  wire block_4;
  wire block_5;
  wire block_6;
  wire block_7;
  wire block_8;
  wire block_9;
  wire block_a;
  wire block_b;
  wire block_c;
  wire block_d;
  wire block_e;
  wire block_f;
  wire blockline;
  assign wirein_readaddr = (((bCtrlState==5))?((wireout_readaddr+1)):(0));
  assign bCKLReadAddr = wireout_readaddr;
  assign bFindLine = wireout_readaddr_delay_1;
  assign wCtrlStateComplete = ((wireout_readaddr_delay_1>24)||(blockline&&(wireout_readaddr>0)));
  assign block_0 = (bCKLReadData [3:0] !=4'b0);
  assign block_1 = (bCKLReadData [7:4] !=4'b0);
  assign block_2 = (bCKLReadData [11:8] !=4'b0);
  assign block_3 = (bCKLReadData [15:12] !=4'b0);
  assign block_4 = (bCKLReadData [19:16] !=4'b0);
  assign block_5 = (bCKLReadData [23:20] !=4'b0);
  assign block_6 = (bCKLReadData [27:24] !=4'b0);
  assign block_7 = (bCKLReadData [31:28] !=4'b0);
  assign block_8 = (bCKLReadData [35:32] !=4'b0);
  assign block_9 = (bCKLReadData [39:36] !=4'b0);
  assign block_a = (bCKLReadData [43:40] !=4'b0);
  assign block_b = (bCKLReadData [47:44] !=4'b0);
  assign block_c = (bCKLReadData [51:48] !=4'b0);
  assign block_d = (bCKLReadData [55:52] !=4'b0);
  assign block_e = (bCKLReadData [59:56] !=4'b0);
  assign block_f = (bCKLReadData [63:60] !=4'b0);
  assign blockline = (block_0&(block_1&(block_2&(block_3&(block_4&(block_5&(block_6&(block_7&(block_8&(block_9&(block_a&(block_b&(block_c&(block_d&(block_e&block_f)))))))))))))));
  hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
  hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
endmodule


(* 
  CLSID = "d6ef2a03-4c58-4b50-a966-44e156694304",
  softmodule = "hdl4se"
*)
module panelinit
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  wInitWrite,
  output  [5:0]  bInitWriteAddr,
  output  [63:0]  bInitWriteData
)
;
  wire [7:0]  wirein_writeaddr;
  wire [7:0]  wireout_writeaddr;
  assign bInitWriteData = 64'h000000000;
  assign wirein_writeaddr = (((bCtrlState==0))?((wireout_writeaddr+1)):(0));
  assign wInitWrite = (wireout_writeaddr<=24);
  assign wCtrlStateComplete = (wireout_writeaddr>24);
  assign bInitWriteAddr = wireout_writeaddr;
  hdl4se_reg #( 6 ) ramwriteaddr( wClk, wirein_writeaddr, wireout_writeaddr );
endmodule


(* 
  CLSID = "abaa9033-f807-4279-93dc-636fd22dcb90",
  softmodule = "hdl4se"
*)
module copylines
(
  input  wClk,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [5:0]  bReadAddr,
  input  [63:0]  bReadData,
  output  wWrite,
  output  [5:0]  bWriteAddr,
  output  [63:0]  bWriteData,
  input  [15:0]  bFromLine
)
;
  wire [7:0]  wirein_readaddr;
  wire [7:0]  wireout_readaddr;
  wire [7:0]  wireout_readaddr_delay_1;
  wire [15:0]  wirein_fromline;
  wire [15:0]  wireout_fromline;
  wire [7:0]  y;
  assign wirein_readaddr = (((bCtrlState==6))?((wireout_readaddr+1)):(0));
  assign wirein_fromline = (((bCtrlState==6))?(bFromLine):(0));
  assign bWriteAddr = (y-1);
  assign bWriteData = bReadData;
  assign wWrite = ((y>=1)&&(y<=24));
  assign wCtrlStateComplete = (y>24);
  assign bReadAddr = (wireout_fromline+wireout_readaddr);
  assign y = (wireout_fromline+wireout_readaddr_delay_1);
  hdl4se_reg #( 6 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
  hdl4se_reg #( 6 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
  hdl4se_reg #( 6 ) reg_fromline( wClk, wirein_fromline, wireout_fromline );
endmodule


module rand
(
  input  wClk,
  output  [15:0]  randnum
)
;
  wire [31:0]  wirein_num;
  wire [31:0]  wireout_num;
  assign randnum = wireout_num [15:0] ;
  assign wirein_num = ((wireout_num*32'd214013)+32'd2531011);
  hdl4se_reg #( 32 ) reg_rand( wClk, wirein_num, wireout_num );
endmodule


module blockshape
(
  input  [3:0]  sel,
  output  [15:0]  blockshape
)
;
  hdl4se_mux16 #( 16 ) mux_blockshape( sel, 1632, 61152, 1568, 1056, 17952
  , 17476, 9792, 1248, 1024, 25120
  , 25664, 61152, 1568, 1056, 25668
  , 17952, blockshape );
endmodule


module genblock
(
  input  wClk,
  input  nwReset,
  input  [3:0]  bCtrlState,
  output  wCtrlStateComplete,
  output  [63:0]  newnextblock
)
;
  wire [6:0]  wirein_genblock_count;
  wire [6:0]  wireout_genblock_count;
  wire wCtrlStateComplete;
  wire [15:0]  randnum;
  wire [3:0]  shapeindex;
  wire [15:0]  shapedata;
  wire [3:0]  colorindex_0;
  wire [3:0]  colorindex;
  wire setshape;
  wire newshape;
  wire [15:0]  wirein_shapedata;
  wire [15:0]  wireout_shapedata;
  wire [15:0]  settoshape;
  wire [63:0]  newblock;
  wire [63:0]  wirein_nextblock;
  wire [63:0]  wireout_nextblock;
  assign wirein_genblock_count = ((((bCtrlState==7)&&(nwReset!=0)))?((wireout_genblock_count+1)):(0));
  assign wCtrlStateComplete = (wireout_genblock_count==18);
  assign wirein_shapedata = ((newshape)?(shapedata):(settoshape));
  assign wirein_nextblock = ((setshape)?(newblock):(wireout_nextblock));
  assign newnextblock = wireout_nextblock;
  assign shapeindex = randnum [3:0] ;
  assign colorindex_0 = randnum [3:0] ;
  assign colorindex = ((((colorindex_0==0)||(colorindex_0==1)))?((colorindex_0+4)):(colorindex_0));
  assign setshape = ((wireout_genblock_count>=2)&&(wireout_genblock_count<=17));
  assign newshape = (wireout_genblock_count==1);
  hdl4se_reg #( 7 ) terris_genblock_count( wClk, wirein_genblock_count, wireout_genblock_count );
  rand randgen( wClk, randnum );
  blockshape shape( shapeindex, shapedata );
  hdl4se_reg #( 16 ) terris_shape( wClk, wirein_shapedata, wireout_shapedata );
  hdl4se_bind2 #( 15, 1 ) nextblockshape( wireout_shapedata [15:1] , wireout_shapedata [0] , settoshape );
  hdl4se_reg #( 64 ) terris_nextblock( wClk, wirein_nextblock, wireout_nextblock );
  hdl4se_bind2 #( 60, 4 ) newnextblock( wireout_nextblock [63:4] , ((wireout_shapedata [0] )?(colorindex):(4'b0000)), newblock );
endmodule


module main
(
  input  wClk,
  input  nwReset,
  output  wWrite,
  output  [31:0]  bWriteAddr,
  output  [31:0]  bWriteData,
  output  [3:0]  bWriteMask,
  output  wRead,
  output  [31:0]  bReadAddr,
  input  [31:0]  bReadData
)
;
  wire wram_Write;
  wire [5:0]  bram_WriteAddr;
  wire [63:0]  bram_WriteData;
  wire [5:0]  bram_ReadAddr;
  wire [63:0]  bram_ReadData;
  wire [31:0]  bCtrlKeyData;
  wire wCtrlStateComplete;
  wire [3:0]  bCtrlState;
  wire [31:0]  bCtrlSpeed;
  wire [31:0]  bCtrlLevel;
  wire [31:0]  bCtrlScore;
  wire [63:0]  bNextBlock;
  wire [63:0]  bCurBlock;
  wire [15:0]  bCurBlockPos;
  wire [31:0]  bResult;
  wire [63:0]  bNewNextBlock;
  wire wGBStateComplete;
  wire [5:0]  bFlushReadAddr;
  wire wFlushCtrlStateComplete;
  wire [5:0]  bBWReadAddr;
  wire [5:0]  bBWWriteAddr;
  wire [63:0]  bBWWriteData;
  wire wBWCtrlStateComplete;
  wire wBWWrite;
  wire [5:0]  bCBWReadAddr;
  wire wCBWCtrlStateComplete;
  wire wCBWCanSetTo;
  wire [5:0]  bCKLReadAddr;
  wire wCKLCtrlStateComplete;
  wire [31:0]  bCKLResult;
  wire [5:0]  bInitWriteAddr;
  wire [63:0]  bInitWriteData;
  wire wInitCtrlStateComplete;
  wire wInitWrite;
  wire [5:0]  bCLReadAddr;
  wire [5:0]  bCLWriteAddr;
  wire [63:0]  bCLWriteData;
  wire wCLCtrlStateComplete;
  wire wCLWrite;
  assign wRead = 1;
  assign bReadAddr = 32'hf0000000;
  assign bCtrlKeyData = bReadData;
  hdl4se_ram1p #( 64, 5 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData
   );
  teris_ctrl ctrl( wClk, nwReset, bCtrlKeyData, wCtrlStateComplete, bCtrlState, bCtrlScore
  , bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock, bCurBlockPos
  , bResult, bNewNextBlock );
  genblock gennewblock( wClk, nwReset, bCtrlState, wGBStateComplete, bNewNextBlock );
  flushtodisp flusher( wClk, bCtrlState, wFlushCtrlStateComplete, bFlushReadAddr, bram_ReadData, wWrite
  , bWriteAddr, bWriteData, bCtrlSpeed, bCtrlLevel, bCtrlScore
  , bNextBlock, bCurBlock, bCurBlockPos );
  blockwrite blockwriter( wClk, bCtrlState, wBWCtrlStateComplete, bBWReadAddr, bram_ReadData, wBWWrite
  , bBWWriteAddr, bBWWriteData, bCurBlock, bCurBlockPos );
  canblocksetto blocksetto( wClk, bCtrlState, wCBWCtrlStateComplete, bCBWReadAddr, bram_ReadData, bCurBlock
  , bCurBlockPos, wCBWCanSetTo );
  checkline checkliner( wClk, bCtrlState, wCKLCtrlStateComplete, bCKLReadAddr, bram_ReadData, bCKLResult
   );
  panelinit initor( wClk, bCtrlState, wInitCtrlStateComplete, wInitWrite, bInitWriteAddr, bInitWriteData
   );
  copylines lineclear( wClk, bCtrlState, wCLCtrlStateComplete, bCLReadAddr, bram_ReadData, wCLWrite
  , bCLWriteAddr, bCLWriteData, bCurBlockPos );
  hdl4se_mux8 #( 32 ) mux_Result( bCtrlState, 32'h0, 32'h0, 32'h0, wCBWCanSetTo, 32'h0
  , bCKLResult, 32'h0, 32'h0, bResult );
  hdl4se_mux8 #( 1 ) mux_Complete( bCtrlState, wInitCtrlStateComplete, wFlushCtrlStateComplete, 0, wCBWCtrlStateComplete, wBWCtrlStateComplete
  , wCKLCtrlStateComplete, wCLCtrlStateComplete, wGBStateComplete, wCtrlStateComplete );
  hdl4se_mux8 #( 1 ) mux_ramWrite( bCtrlState, wInitWrite, 0, 0, 0, wBWWrite
  , 0, wCLWrite, 0, wram_Write );
  hdl4se_mux8 #( 6 ) mux_ramWriteAddr( bCtrlState, bInitWriteAddr, 0, 0, 0, bBWWriteAddr
  , 0, bCLWriteAddr, 0, bram_WriteAddr );
  hdl4se_mux8 #( 64 ) mux_ramWriteData( bCtrlState, bInitWriteData, 64'h000000000, 64'h000000000, 64'h000000000, bBWWriteData
  , 64'h000000000, bCLWriteData, 64'h000000000, bram_WriteData );
  hdl4se_mux8 #( 6 ) mux_ramReadAddr( bCtrlState, 0, bFlushReadAddr, 0, bCBWReadAddr, bBWReadAddr
  , bCKLReadAddr, bCLReadAddr, 0, bram_ReadAddr );
endmodule


(* 
  HDL4SE = "LCOM",
  CLSID = "81de7969-f783-4023-bde6-f815f8d59c05",
  softmodule = "hdl4se"
*)
module terrisdevice
(
  input  wClk,
  input  nwReset,
  input  wWrite,
  input  [31:0]  bWriteAddr,
  input  [31:0]  bWriteData,
  input  [3:0]  bWriteMask,
  input  wRead,
  input  [31:0]  bReadAddr,
  output  [31:0]  bReadData
)
;
endmodule


module top
(
  input  wClk,
  input  nwReset
)
;
  wire wWrite;
  wire wRead;
  wire [31:0]  bWriteAddr;
  wire [31:0]  bWriteData;
  wire [31:0]  bReadAddr;
  wire [31:0]  bReadData;
  wire [3:0]  bWriteMask;
  terrisdevice terrisui( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
  , wRead, bReadAddr, bReadData );
  main terrisctrl( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
  , wRead, bReadAddr, bReadData );
endmodule