* Only ssip in sip is writeable in smode
* Add sip write permission check
* Fix mipReg write logic

In this commit, we add License for XiangShan project. 

* backend,RS: add numEnq parameter to allow multiple enqueue instructions

* backend,RS: support multiple issue instructions at each cycle

This commit adds a new AXI4 device to generate external interrupts.
Previously none of the simulated external devices trigger interrupts.
To test external interrupts, we add this device.

* Update mill and rocket-chip

* [WIP] auto generate dts by diplomacy

* PTW: fix typo

* PTW: add perf for req's count & cycle

README.md: fix example commands

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite ptw for multi req support

* PTW: remove some assert, fix level init bug

* PTW: itlb has highter priority than dtlb

* PTW: fix bug that mix cache's resp logic

* PTW: fix stupid bug that mix .U and .W

* PTW: replay will not be blocked if fsm empty

* PTW: miss queue req may return miss queue

In the before design, only miss queue req can go into
fsm, and would not be blocked.
Now, to simplify design, miss queue req are just the
same with new req, may blocked, going to fsm or miss queue.

* PTW: fix ptw filter iss valid bug

* PTW.fsm: fix bug that should not mem.req when sfenceLatch

* PTW: fix ptw sfenceLatch's bug

* PTW: add some perf counters

* PTW: fix bug in filter enq ptr logic

* PTW: fix bug of sfence in ptw

* test: add current branch to ci-test, tmp

* PTW: fix bug of cache's hit logic and fsm's pf

* PTW: fix bug of filter's enq and block* signal

* PTW: fix bug of filter's pteResp filter

* PTW: add some assert of filter's counter

* PTW: fix bug of filter's enq logic

* PTW: set PTWMSHRSIZE 16

* PTW: fix naive perf counter's bug

* PTW: set PTWMSHRSIZE 8

* PTW: set PTWMSHRSIZE 32

* Revert "PTW: set PTWMSHRSIZE 32"

This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.

* Revert "test: add current branch to ci-test, tmp"

This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d1

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt).
Should be easier for RS.

Config: add MinimalConfig

* CI: put perf result in xs-perf/cmtsha-time

* CI: make result dir before start perfing

* Update emu.yml

* ci: add bash scripts

* scripts: add xiangshan wrapper
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

This commit adds support for using Synopsys VCS to simulate SimTop.
Difftest is also supported.

For now, we use src/test/vsrc/vcs/top.v as the top-level module.
In the future, we may support VCS slave mode for better scalability.

MinimalConfig limited queues' size, disabled TAGE to limit generated
verilog size

Usage: change `config = DefaultConfig` to `config = MinimalConfig`
in Top.scala / SimTop.scala

* [WIP] Backend: add mul to fast wake-up

* Backend: handle mul wb priority and fix wrong delay

* RS: devide fastwakeup and nonBlocked(they were binded)

This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot.
Previously the tailPtr becomes size.U when there're no instructions before headPtr. It works fine
when DispatchQueueSize is power2.

This commit uses Vec for lsrc, psrc, srcState and srcType in MicroOp bundle.
This makes uop easier to access.

* emu: add --no-perf-counter option

Now perf counter result print will no longer be controlled by
--log-begin / --log-end

* emu: add --force-dump-result option

This option will override log_end to -1 when simulation finishs.
--no-perf-counter option is removed.

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* StoreQueue: add sbuffer enq condition assertion

Store data op (std) may still be invalid after store addr op's (sta)
commitment, so datavalid needs to be checked before commiting
store data to sbuffer

Note that at current commit a non-completed std op for a
commited store may exist. We should make sure that uop
will not be cancelled by a latter branch mispredict. More work
to be done!

* Roq: add std/sta split writeback logic

Now store will commit only if both sta & std have been writebacked
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

* difftest: revise coreid assignment

* nemuproxy: compatible for smp difftest

* difftest: fix goldenMem initialization problem

* difftest: goldenMem update works

* difftest: api compatible for modified nemu

* difftest: support load check for smp difftest
* verification is required later

* misc: remove unused xstrap wiring

* Remove unused code

* difftest: add latch for difftest-loadevent

* misc: update inclusivecache

* difftest: reset resp for sbuffer & atomic-unit to avoid duplicate update
of goldenMem

* difftest: dump coreid when difftest failed

* difftest: dump corresponding memory of another core when smp difftest failed
* Only works for dual-core

* difftest: fix interrupt handler

* difftest: cleanup code

* roq: remove legacy signal for difftest

* Perf: add perf counter for addr gen,  across page or not

* Perf: add perf counter for addr gen, just record first issue

Pipe causes the return value of make command ignored. Pipe is disabled for
cpp compilation output until we find an elegant solution to exit on errors.