icache: fix conflict with master``

Icache add mmio support for flash instruction fetch

backend: bug fixes for exception-related logic in Roq and CSR

icache: add not bus-width aligned MMIO req support

IFU: add mmio aligned function

If we DontCare a register write data, chisel will convert it to 0 (or somthing else?).
Thus, for exceptionVec, we cannot simply DontCare the wdata.
Instead, we have to assign them separately.

Opt fmisc timing

bug fixes in TLB, PTW and sbuffer

s2_hit use s3_valid :)

LoadQueue: opt writeback select timing

sbuffer: add sq empty check

icache: fix ipf bug

Perf: Modify predictor counter logic

When sbuffer checks if it is empty, it needs to check if sq is also empty
so there is no pending store. Errors will emerge rarely if we do not
check sq.

Previously, we only give the first instrcution to backend when the
packet causes a page fault. It will be stuck if not because waymask is 0
because no hit but hit includes ipf. So we seperates them.

exception and mmio judgement is done in tlb according to paddr. icache
send mmio request to Instruction uncache module. It send TileLink GET to
peripherals like flash and receive instructions per beat.

* Gen selectMask in 2nd cycle, in parallel with DeqMask

lock-emu: add ‘\0’ to user's tail to avoid gibberish

We used to select writeback inst and update writebacked bit
at the same cycle. However, it is too long to finish in one cycle.

Now we select writeback inst and gen wbSelectedMask in cycle 1,
then we use RegNext(wbSelectedMask) and writeback bit to select
inst in the next cycle.

core: optimize exceptionVec usages